mcu_sram_test.map.qmsg

verilog编写基于FPGA的示波器核心实现

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mfreq mfreq:freq8 " "Info: Elaborating entity \"mfreq\" for hierarchy \"mfreq:freq8\"" {  } { { "mcu_sram_test.bdf" "freq8" { Schematic "F:/fpga test/fpge示波器/mcu_sram beta1.1/mcu_sram_test.bdf" { { 120 -72 48 216 "freq8" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 mfreq.v(17) " "Warning (10230): Verilog HDL assignment warning at mfreq.v(17): truncated value with size 32 to match size of target (8)" {  } { { "mfreq.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/mfreq.v" 17 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "osc:inst2\|osc_display:inst3\|xbuf\[0\] data_in GND " "Warning: Reduced register \"osc:inst2\|osc_display:inst3\|xbuf\[0\]\" with stuck data_in port to stuck value GND" {  } { { "osc_display.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc_display.v" 115 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "osc:inst2\|osc_display:inst3\|ybuf\[7\] data_in GND " "Warning: Reduced register \"osc:inst2\|osc_display:inst3\|ybuf\[7\]\" with stuck data_in port to stuck value GND" {  } { { "osc_display.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc_display.v" 115 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "osc:inst2\|osc_display:inst3\|ybuf\[0\] data_in GND " "Warning: Reduced register \"osc:inst2\|osc_display:inst3\|ybuf\[0\]\" with stuck data_in port to stuck value GND" {  } { { "osc_display.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc_display.v" 115 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "osc:inst2\|osc_display:inst3\|link_yout osc:inst2\|osc_display:inst3\|link_xout " "Info: Duplicate register \"osc:inst2\|osc_display:inst3\|link_yout\" merged to single register \"osc:inst2\|osc_display:inst3\|link_xout\"" {  } { { "osc_display.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc_display.v" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "mcu_fpga_control:inst8\|rd_state_s\[0\] mcu_fpga_control:inst8\|link_rd_data_low " "Info: Duplicate register \"mcu_fpga_control:inst8\|rd_state_s\[0\]\" merged to single register \"mcu_fpga_control:inst8\|link_rd_data_low\"" {  } { { "mcu_fpga_control.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/mcu_fpga_control.v" 124 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "osc:inst2\|osc_display:inst3\|da_wry osc:inst2\|osc_display:inst3\|da_wrx " "Info: Duplicate register \"osc:inst2\|osc_display:inst3\|da_wry\" merged to single register \"osc:inst2\|osc_display:inst3\|da_wrx\"" {  } { { "osc_display.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc_display.v" 17 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|mcu_sram_test\|osc:inst2\|osc_control:inst\|state 4 " "Info: State machine \"\|mcu_sram_test\|osc:inst2\|osc_control:inst\|state\" contains 4 states" {  } { { "osc_control.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc_control.v" 28 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|mcu_sram_test\|osc:inst2\|osc_display:inst3\|state 7 " "Info: State machine \"\|mcu_sram_test\|osc:inst2\|osc_display:inst3\|state\" contains 7 states" {  } { { "osc_display.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc_display.v" 36 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|mcu_sram_test\|sram_control:inst4\|state 6 " "Info: State machine \"\|mcu_sram_test\|sram_control:inst4\|state\" contains 6 states" {  } { { "sram_control.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/sram_control.v" 57 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|mcu_sram_test\|mcu_fpga_control:inst8\|rd_state 4 " "Info: State machine \"\|mcu_sram_test\|mcu_fpga_control:inst8\|rd_state\" contains 4 states" {  } { { "mcu_fpga_control.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/mcu_fpga_control.v" 74 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|mcu_sram_test\|mcu_fpga_control:inst8\|wr_state 4 " "Info: State machine \"\|mcu_sram_test\|mcu_fpga_control:inst8\|wr_state\" contains 4 states" {  } { { "mcu_fpga_control.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/mcu_fpga_control.v" 68 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|mcu_sram_test\|mcu_fpga_control:inst8\|wr_ca_state 3 " "Info: State machine \"\|mcu_sram_test\|mcu_fpga_control:inst8\|wr_ca_state\" contains 3 states" {  } { { "mcu_fpga_control.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/mcu_fpga_control.v" 307 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|mcu_sram_test\|mcu_fpga_control:inst8\|wr_dsram_state 3 " "Info: State machine \"\|mcu_sram_test\|mcu_fpga_control:inst8\|wr_dsram_state\" contains 3 states" {  } { { "mcu_fpga_control.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/mcu_fpga_control.v" 307 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|mcu_sram_test\|mcu_fpga_control:inst8\|wr_ad_state 3 " "Info: State machine \"\|mcu_sram_test\|mcu_fpga_control:inst8\|wr_ad_state\" contains 3 states" {  } { { "mcu_fpga_control.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/mcu_fpga_control.v" 307 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|mcu_sram_test\|mcu_fpga_control:inst8\|rd_ca_state 3 " "Info: State machine \"\|mcu_sram_test\|mcu_fpga_control:inst8\|rd_ca_state\" contains 3 states" {  } { { "mcu_fpga_control.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/mcu_fpga_control.v" 308 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|mcu_sram_test\|mcu_fpga_control:inst8\|rd_dsram_state 3 " "Info: State machine \"\|mcu_sram_test\|mcu_fpga_control:inst8\|rd_dsram_state\" contains 3 states" {  } { { "mcu_fpga_control.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/mcu_fpga_control.v" 308 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|mcu_sram_test\|mcu_fpga_control:inst8\|dds_phase_state 3 " "Info: State machine \"\|mcu_sram_test\|mcu_fpga_control:inst8\|dds_phase_state\" contains 3 states" {  } { { "mcu_fpga_control.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/mcu_fpga_control.v" 309 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|mcu_sram_test\|mcu_fpga_control:inst8\|dds_freq_state 3 " "Info: State machine \"\|mcu_sram_test\|mcu_fpga_control:inst8\|dds_freq_state\" contains 3 states" {  } { { "mcu_fpga_control.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/mcu_fpga_control.v" 309 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}