mcu_sram_test.map.qmsg

verilog编写基于FPGA的示波器核心实现

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mux mux_sram:inst\|lpm_mux:lpm_mux_component " "Info: Elaborating entity \"lpm_mux\" for hierarchy \"mux_sram:inst\|lpm_mux:lpm_mux_component\"" {  } { { "mux_sram.v" "lpm_mux_component" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/mux_sram.v" 65 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "mux_sram:inst\|lpm_mux:lpm_mux_component " "Info: Elaborated megafunction instantiation \"mux_sram:inst\|lpm_mux:lpm_mux_component\"" {  } { { "mux_sram.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/mux_sram.v" 65 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_pgc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_pgc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_pgc " "Info: Found entity 1: mux_pgc" {  } { { "db/mux_pgc.tdf" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/db/mux_pgc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_pgc mux_sram:inst\|lpm_mux:lpm_mux_component\|mux_pgc:auto_generated " "Info: Elaborating entity \"mux_pgc\" for hierarchy \"mux_sram:inst\|lpm_mux:lpm_mux_component\|mux_pgc:auto_generated\"" {  } { { "lpm_mux.tdf" "auto_generated" { Text "f:/altera/quartus60/libraries/megafunctions/lpm_mux.tdf" 84 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "osc osc:inst2 " "Info: Elaborating entity \"osc\" for hierarchy \"osc:inst2\"" {  } { { "mcu_sram_test.bdf" "inst2" { Schematic "F:/fpga test/fpge示波器/mcu_sram beta1.1/mcu_sram_test.bdf" { { 24 216 400 184 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "osc_display osc:inst2\|osc_display:inst3 " "Info: Elaborating entity \"osc_display\" for hierarchy \"osc:inst2\|osc_display:inst3\"" {  } { { "osc.bdf" "inst3" { Schematic "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc.bdf" { { 112 792 976 240 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "COMPARE6 osc_display.v(31) " "Warning (10036): Verilog HDL or VHDL warning at osc_display.v(31): object \"COMPARE6\" assigned a value but never read" {  } { { "osc_display.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc_display.v" 31 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "COMPARE7 osc_display.v(32) " "Warning (10036): Verilog HDL or VHDL warning at osc_display.v(32): object \"COMPARE7\" assigned a value but never read" {  } { { "osc_display.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc_display.v" 32 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "COMPARE8 osc_display.v(33) " "Warning (10036): Verilog HDL or VHDL warning at osc_display.v(33): object \"COMPARE8\" assigned a value but never read" {  } { { "osc_display.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc_display.v" 33 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 osc_display.v(60) " "Warning (10230): Verilog HDL assignment warning at osc_display.v(60): truncated value with size 32 to match size of target (3)" {  } { { "osc_display.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc_display.v" 60 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "osc_display.v(57) " "Info (10264): Verilog HDL Case Statement information at osc_display.v(57): all case item expressions in this case statement are onehot" {  } { { "osc_display.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc_display.v" 57 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "osc_ram osc:inst2\|osc_ram:inst2 " "Info: Elaborating entity \"osc_ram\" for hierarchy \"osc:inst2\|osc_ram:inst2\"" {  } { { "osc.bdf" "inst2" { Schematic "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc.bdf" { { 88 512 768 248 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../altera/quartus60/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus60/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 426 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram osc:inst2\|osc_ram:inst2\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"osc:inst2\|osc_ram:inst2\|altsyncram:altsyncram_component\"" {  } { { "osc_ram.v" "altsyncram_component" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc_ram.v" 75 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "osc:inst2\|osc_ram:inst2\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"osc:inst2\|osc_ram:inst2\|altsyncram:altsyncram_component\"" {  } { { "osc_ram.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc_ram.v" 75 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_usp1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_usp1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_usp1 " "Info: Found entity 1: altsyncram_usp1" {  } { { "db/altsyncram_usp1.tdf" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/db/altsyncram_usp1.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_usp1 osc:inst2\|osc_ram:inst2\|altsyncram:altsyncram_component\|altsyncram_usp1:auto_generated " "Info: Elaborating entity \"altsyncram_usp1\" for hierarchy \"osc:inst2\|osc_ram:inst2\|altsyncram:altsyncram_component\|altsyncram_usp1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "f:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "osc_control osc:inst2\|osc_control:inst " "Info: Elaborating entity \"osc_control\" for hierarchy \"osc:inst2\|osc_control:inst\"" {  } { { "osc.bdf" "inst" { Schematic "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc.bdf" { { 104 184 400 232 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "osc_control.v(39) " "Info (10264): Verilog HDL Case Statement information at osc_control.v(39): all case item expressions in this case statement are onehot" {  } { { "osc_control.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc_control.v" 39 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}