mcu_sram_test.map.qmsg

verilog编写基于FPGA的示波器核心实现

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sram_control.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file sram_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 sram_control " "Info: Found entity 1: sram_control" {  } { { "sram_control.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/sram_control.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "just看看.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file just看看.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 just看看 " "Info: Found entity 1: just看看" {  } { { "just看看.bdf" "" { Schematic "F:/fpga test/fpge示波器/mcu_sram beta1.1/just看看.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dds_control.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file dds_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 dds_control " "Info: Found entity 1: dds_control" {  } { { "dds_control.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/dds_control.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dds.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file dds.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 dds " "Info: Found entity 1: dds" {  } { { "dds.bdf" "" { Schematic "F:/fpga test/fpge示波器/mcu_sram beta1.1/dds.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "osc.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file osc.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 osc " "Info: Found entity 1: osc" {  } { { "osc.bdf" "" { Schematic "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "osc_control.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file osc_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 osc_control " "Info: Found entity 1: osc_control" {  } { { "osc_control.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc_control.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "osc_display.v(38) " "Warning (10273): Verilog HDL warning at osc_display.v(38): extended using \"x\" or \"z\"" {  } { { "osc_display.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc_display.v" 38 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "osc_display.v(39) " "Warning (10273): Verilog HDL warning at osc_display.v(39): extended using \"x\" or \"z\"" {  } { { "osc_display.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc_display.v" 39 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "osc_display.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file osc_display.v" { { "Info" "ISGN_ENTITY_NAME" "1 osc_display " "Info: Found entity 1: osc_display" {  } { { "osc_display.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc_display.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mfreq.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file mfreq.v" { { "Info" "ISGN_ENTITY_NAME" "1 mfreq " "Info: Found entity 1: mfreq" {  } { { "mfreq.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/mfreq.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "osc_ram.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file osc_ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 osc_ram " "Info: Found entity 1: osc_ram" {  } { { "osc_ram.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc_ram.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "mcu_sram_test " "Info: Elaborating entity \"mcu_sram_test\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mcu_fpga_control mcu_fpga_control:inst8 " "Info: Elaborating entity \"mcu_fpga_control\" for hierarchy \"mcu_fpga_control:inst8\"" {  } { { "mcu_sram_test.bdf" "inst8" { Schematic "F:/fpga test/fpge示波器/mcu_sram beta1.1/mcu_sram_test.bdf" { { -472 160 368 -184 "inst8" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "mcu_fpga_control.v(94) " "Info (10264): Verilog HDL Case Statement information at mcu_fpga_control.v(94): all case item expressions in this case statement are onehot" {  } { { "mcu_fpga_control.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/mcu_fpga_control.v" 94 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "mcu_fpga_control.v(138) " "Info (10264): Verilog HDL Case Statement information at mcu_fpga_control.v(138): all case item expressions in this case statement are onehot" {  } { { "mcu_fpga_control.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/mcu_fpga_control.v" 138 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sram_control sram_control:inst4 " "Info: Elaborating entity \"sram_control\" for hierarchy \"sram_control:inst4\"" {  } { { "mcu_sram_test.bdf" "inst4" { Schematic "F:/fpga test/fpge示波器/mcu_sram beta1.1/mcu_sram_test.bdf" { { -456 504 720 -232 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "sram_control.v(92) " "Info (10264): Verilog HDL Case Statement information at sram_control.v(92): all case item expressions in this case statement are onehot" {  } { { "sram_control.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/sram_control.v" 92 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_sram mux_sram:inst " "Info: Elaborating entity \"mux_sram\" for hierarchy \"mux_sram:inst\"" {  } { { "mcu_sram_test.bdf" "inst" { Schematic "F:/fpga test/fpge示波器/mcu_sram beta1.1/mcu_sram_test.bdf" { { -688 464 616 -608 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../altera/quartus60/libraries/megafunctions/lpm_mux.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus60/libraries/megafunctions/lpm_mux.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mux " "Info: Found entity 1: lpm_mux" {  } { { "lpm_mux.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/lpm_mux.tdf" 72 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}