mcu_sram_test.hier_info

verilog编写基于FPGA的示波器核心实现

address_a[4] => altsyncram_usp1:auto_generated.address_a[4]
address_a[5] => altsyncram_usp1:auto_generated.address_a[5]
address_a[6] => altsyncram_usp1:auto_generated.address_a[6]
address_a[7] => altsyncram_usp1:auto_generated.address_a[7]
address_a[8] => altsyncram_usp1:auto_generated.address_a[8]
address_a[9] => altsyncram_usp1:auto_generated.address_a[9]
address_b[0] => altsyncram_usp1:auto_generated.address_b[0]
address_b[1] => altsyncram_usp1:auto_generated.address_b[1]
address_b[2] => altsyncram_usp1:auto_generated.address_b[2]
address_b[3] => altsyncram_usp1:auto_generated.address_b[3]
address_b[4] => altsyncram_usp1:auto_generated.address_b[4]
address_b[5] => altsyncram_usp1:auto_generated.address_b[5]
address_b[6] => altsyncram_usp1:auto_generated.address_b[6]
address_b[7] => altsyncram_usp1:auto_generated.address_b[7]
address_b[8] => altsyncram_usp1:auto_generated.address_b[8]
address_b[9] => altsyncram_usp1:auto_generated.address_b[9]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_usp1:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= <GND>
q_a[1] <= <GND>
q_a[2] <= <GND>
q_a[3] <= <GND>
q_a[4] <= <GND>
q_a[5] <= <GND>
q_a[6] <= <GND>
q_a[7] <= <GND>
q_b[0] <= altsyncram_usp1:auto_generated.q_b[0]
q_b[1] <= altsyncram_usp1:auto_generated.q_b[1]
q_b[2] <= altsyncram_usp1:auto_generated.q_b[2]
q_b[3] <= altsyncram_usp1:auto_generated.q_b[3]
q_b[4] <= altsyncram_usp1:auto_generated.q_b[4]
q_b[5] <= altsyncram_usp1:auto_generated.q_b[5]
q_b[6] <= altsyncram_usp1:auto_generated.q_b[6]
q_b[7] <= altsyncram_usp1:auto_generated.q_b[7]


|mcu_sram_test|osc:inst2|osc_ram:inst2|altsyncram:altsyncram_component|altsyncram_usp1:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9
address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
address_b[0] => ram_block1a0.PORTBADDR
address_b[0] => ram_block1a1.PORTBADDR
address_b[0] => ram_block1a2.PORTBADDR
address_b[0] => ram_block1a3.PORTBADDR
address_b[0] => ram_block1a4.PORTBADDR
address_b[0] => ram_block1a5.PORTBADDR
address_b[0] => ram_block1a6.PORTBADDR
address_b[0] => ram_block1a7.PORTBADDR
address_b[1] => ram_block1a0.PORTBADDR1
address_b[1] => ram_block1a1.PORTBADDR1
address_b[1] => ram_block1a2.PORTBADDR1
address_b[1] => ram_block1a3.PORTBADDR1
address_b[1] => ram_block1a4.PORTBADDR1
address_b[1] => ram_block1a5.PORTBADDR1
address_b[1] => ram_block1a6.PORTBADDR1
address_b[1] => ram_block1a7.PORTBADDR1
address_b[2] => ram_block1a0.PORTBADDR2
address_b[2] => ram_block1a1.PORTBADDR2
address_b[2] => ram_block1a2.PORTBADDR2
address_b[2] => ram_block1a3.PORTBADDR2
address_b[2] => ram_block1a4.PORTBADDR2
address_b[2] => ram_block1a5.PORTBADDR2
address_b[2] => ram_block1a6.PORTBADDR2
address_b[2] => ram_block1a7.PORTBADDR2
address_b[3] => ram_block1a0.PORTBADDR3
address_b[3] => ram_block1a1.PORTBADDR3
address_b[3] => ram_block1a2.PORTBADDR3
address_b[3] => ram_block1a3.PORTBADDR3
address_b[3] => ram_block1a4.PORTBADDR3
address_b[3] => ram_block1a5.PORTBADDR3
address_b[3] => ram_block1a6.PORTBADDR3
address_b[3] => ram_block1a7.PORTBADDR3
address_b[4] => ram_block1a0.PORTBADDR4
address_b[4] => ram_block1a1.PORTBADDR4
address_b[4] => ram_block1a2.PORTBADDR4
address_b[4] => ram_block1a3.PORTBADDR4
address_b[4] => ram_block1a4.PORTBADDR4
address_b[4] => ram_block1a5.PORTBADDR4
address_b[4] => ram_block1a6.PORTBADDR4
address_b[4] => ram_block1a7.PORTBADDR4
address_b[5] => ram_block1a0.PORTBADDR5
address_b[5] => ram_block1a1.PORTBADDR5
address_b[5] => ram_block1a2.PORTBADDR5
address_b[5] => ram_block1a3.PORTBADDR5
address_b[5] => ram_block1a4.PORTBADDR5
address_b[5] => ram_block1a5.PORTBADDR5
address_b[5] => ram_block1a6.PORTBADDR5
address_b[5] => ram_block1a7.PORTBADDR5
address_b[6] => ram_block1a0.PORTBADDR6
address_b[6] => ram_block1a1.PORTBADDR6
address_b[6] => ram_block1a2.PORTBADDR6
address_b[6] => ram_block1a3.PORTBADDR6
address_b[6] => ram_block1a4.PORTBADDR6
address_b[6] => ram_block1a5.PORTBADDR6
address_b[6] => ram_block1a6.PORTBADDR6
address_b[6] => ram_block1a7.PORTBADDR6
address_b[7] => ram_block1a0.PORTBADDR7
address_b[7] => ram_block1a1.PORTBADDR7
address_b[7] => ram_block1a2.PORTBADDR7
address_b[7] => ram_block1a3.PORTBADDR7
address_b[7] => ram_block1a4.PORTBADDR7
address_b[7] => ram_block1a5.PORTBADDR7
address_b[7] => ram_block1a6.PORTBADDR7
address_b[7] => ram_block1a7.PORTBADDR7
address_b[8] => ram_block1a0.PORTBADDR8
address_b[8] => ram_block1a1.PORTBADDR8
address_b[8] => ram_block1a2.PORTBADDR8
address_b[8] => ram_block1a3.PORTBADDR8
address_b[8] => ram_block1a4.PORTBADDR8
address_b[8] => ram_block1a5.PORTBADDR8
address_b[8] => ram_block1a6.PORTBADDR8
address_b[8] => ram_block1a7.PORTBADDR8
address_b[9] => ram_block1a0.PORTBADDR9
address_b[9] => ram_block1a1.PORTBADDR9
address_b[9] => ram_block1a2.PORTBADDR9
address_b[9] => ram_block1a3.PORTBADDR9
address_b[9] => ram_block1a4.PORTBADDR9
address_b[9] => ram_block1a5.PORTBADDR9
address_b[9] => ram_block1a6.PORTBADDR9
address_b[9] => ram_block1a7.PORTBADDR9
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a0.CLK1
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a1.CLK1
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a2.CLK1
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a3.CLK1
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a4.CLK1
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a5.CLK1
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a6.CLK1
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a7.CLK1
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
q_b[0] <= ram_block1a0.PORTBDATAOUT
q_b[1] <= ram_block1a1.PORTBDATAOUT
q_b[2] <= ram_block1a2.PORTBDATAOUT
q_b[3] <= ram_block1a3.PORTBDATAOUT
q_b[4] <= ram_block1a4.PORTBDATAOUT
q_b[5] <= ram_block1a5.PORTBDATAOUT
q_b[6] <= ram_block1a6.PORTBDATAOUT
q_b[7] <= ram_block1a7.PORTBDATAOUT
rden_b => ram_block1a0.PORTBRE
rden_b => ram_block1a1.PORTBRE
rden_b => ram_block1a2.PORTBRE
rden_b => ram_block1a3.PORTBRE
rden_b => ram_block1a4.PORTBRE
rden_b => ram_block1a5.PORTBRE
rden_b => ram_block1a6.PORTBRE
rden_b => ram_block1a7.PORTBRE
wren_a => ram_block1a0.ENA0
wren_a => ram_block1a1.ENA0
wren_a => ram_block1a2.ENA0
wren_a => ram_block1a3.ENA0
wren_a => ram_block1a4.ENA0
wren_a => ram_block1a5.ENA0
wren_a => ram_block1a6.ENA0
wren_a => ram_block1a7.ENA0


|mcu_sram_test|osc:inst2|osc_control:inst
oscaddrin[0] => ADDROUT[0]~reg0.DATAIN
oscaddrin[1] => ADDROUT[1]~reg0.DATAIN
oscaddrin[2] => ADDROUT[2]~reg0.DATAIN
oscaddrin[3] => ADDROUT[3]~reg0.DATAIN
oscaddrin[4] => ~NO_FANOUT~
oscaddrin[5] => ~NO_FANOUT~
oscaddrin[6] => ~NO_FANOUT~
oscaddrin[7] => ~NO_FANOUT~
oscaddrin[8] => ADDROUT[4]~reg0.DATAIN
oscaddrin[9] => ADDROUT[5]~reg0.DATAIN
oscaddrin[10] => ADDROUT[6]~reg0.DATAIN
oscaddrin[11] => ADDROUT[7]~reg0.DATAIN
oscaddrin[12] => ADDROUT[8]~reg0.DATAIN
oscaddrin[13] => ADDROUT[9]~reg0.DATAIN
oscaddrin[14] => ~NO_FANOUT~
oscaddrin[15] => ~NO_FANOUT~
oscaddrin[16] => ~NO_FANOUT~
oscdatain[0] => DATAOUT[0]~reg0.DATAIN
oscdatain[1] => DATAOUT[1]~reg0.DATAIN
oscdatain[2] => DATAOUT[2]~reg0.DATAIN
oscdatain[3] => DATAOUT[3]~reg0.DATAIN
oscdatain[4] => DATAOUT[4]~reg0.DATAIN
oscdatain[5] => DATAOUT[5]~reg0.DATAIN
oscdatain[6] => DATAOUT[6]~reg0.DATAIN
oscdatain[7] => DATAOUT[7]~reg0.DATAIN
oscdatain[8] => ~NO_FANOUT~
oscdatain[9] => ~NO_FANOUT~
oscdatain[10] => ~NO_FANOUT~
oscdatain[11] => ~NO_FANOUT~
oscdatain[12] => ~NO_FANOUT~
oscdatain[13] => ~NO_FANOUT~
oscdatain[14] => ~NO_FANOUT~
oscdatain[15] => ~NO_FANOUT~
osc_sig => state~0.DATAB
osc_sig => Selector0.IN2
cs => wren~1.OUTPUTSELECT
cs => rden~0.OUTPUTSELECT
cs => state~2.OUTPUTSELECT
cs => state~3.OUTPUTSELECT
cs => state~4.OUTPUTSELECT
cs => state~5.OUTPUTSELECT
clk => rden~reg0.CLK
clk => ADDROUT[9]~reg0.CLK
clk => ADDROUT[8]~reg0.CLK
clk => ADDROUT[7]~reg0.CLK
clk => ADDROUT[6]~reg0.CLK
clk => ADDROUT[5]~reg0.CLK
clk => ADDROUT[4]~reg0.CLK
clk => ADDROUT[3]~reg0.CLK
clk => ADDROUT[2]~reg0.CLK
clk => ADDROUT[1]~reg0.CLK
clk => ADDROUT[0]~reg0.CLK
clk => DATAOUT[7]~reg0.CLK
clk => DATAOUT[6]~reg0.CLK
clk => DATAOUT[5]~reg0.CLK
clk => DATAOUT[4]~reg0.CLK
clk => DATAOUT[3]~reg0.CLK
clk => DATAOUT[2]~reg0.CLK
clk => DATAOUT[1]~reg0.CLK
clk => DATAOUT[0]~reg0.CLK
clk => wren~reg0.CLK
clk => state~6.IN1
ADDROUT[0] <= ADDROUT[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDROUT[1] <= ADDROUT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDROUT[2] <= ADDROUT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDROUT[3] <= ADDROUT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDROUT[4] <= ADDROUT[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDROUT[5] <= ADDROUT[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDROUT[6] <= ADDROUT[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDROUT[7] <= ADDROUT[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDROUT[8] <= ADDROUT[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDROUT[9] <= ADDROUT[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DATAOUT[0] <= DATAOUT[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DATAOUT[1] <= DATAOUT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DATAOUT[2] <= DATAOUT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DATAOUT[3] <= DATAOUT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DATAOUT[4] <= DATAOUT[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DATAOUT[5] <= DATAOUT[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DATAOUT[6] <= DATAOUT[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DATAOUT[7] <= DATAOUT[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rden <= rden~reg0.DB_MAX_OUTPUT_PORT_TYPE
wren <= wren~reg0.DB_MAX_OUTPUT_PORT_TYPE


|mcu_sram_test|mfreq:freq8
clk_in => count[6].CLK
clk_in => count[5].CLK
clk_in => count[4].CLK
clk_in => count[3].CLK
clk_in => count[2].CLK
clk_in => count[1].CLK
clk_in => count[0].CLK
clk_in => count[7].CLK
clk_out <= count[2].DB_MAX_OUTPUT_PORT_TYPE