mcu_sram_test.hier_info

verilog编写基于FPGA的示波器核心实现

data0x[10] => sub_wire4[10].IN1
data0x[11] => sub_wire4[11].IN1
data0x[12] => sub_wire4[12].IN1
data0x[13] => sub_wire4[13].IN1
data0x[14] => sub_wire4[14].IN1
data0x[15] => sub_wire4[15].IN1
data1x[0] => sub_wire4[16].IN1
data1x[1] => sub_wire4[17].IN1
data1x[2] => sub_wire4[18].IN1
data1x[3] => sub_wire4[19].IN1
data1x[4] => sub_wire4[20].IN1
data1x[5] => sub_wire4[21].IN1
data1x[6] => sub_wire4[22].IN1
data1x[7] => sub_wire4[23].IN1
data1x[8] => sub_wire4[24].IN1
data1x[9] => sub_wire4[25].IN1
data1x[10] => sub_wire4[26].IN1
data1x[11] => sub_wire4[27].IN1
data1x[12] => sub_wire4[28].IN1
data1x[13] => sub_wire4[29].IN1
data1x[14] => sub_wire4[30].IN1
data1x[15] => sub_wire4[31].IN1
sel => sub_wire2.IN1
result[0] <= lpm_mux:lpm_mux_component.result
result[1] <= lpm_mux:lpm_mux_component.result
result[2] <= lpm_mux:lpm_mux_component.result
result[3] <= lpm_mux:lpm_mux_component.result
result[4] <= lpm_mux:lpm_mux_component.result
result[5] <= lpm_mux:lpm_mux_component.result
result[6] <= lpm_mux:lpm_mux_component.result
result[7] <= lpm_mux:lpm_mux_component.result
result[8] <= lpm_mux:lpm_mux_component.result
result[9] <= lpm_mux:lpm_mux_component.result
result[10] <= lpm_mux:lpm_mux_component.result
result[11] <= lpm_mux:lpm_mux_component.result
result[12] <= lpm_mux:lpm_mux_component.result
result[13] <= lpm_mux:lpm_mux_component.result
result[14] <= lpm_mux:lpm_mux_component.result
result[15] <= lpm_mux:lpm_mux_component.result


|mcu_sram_test|mux_sram:inst|lpm_mux:lpm_mux_component
data[0][0] => mux_pgc:auto_generated.data[0]
data[0][1] => mux_pgc:auto_generated.data[1]
data[0][2] => mux_pgc:auto_generated.data[2]
data[0][3] => mux_pgc:auto_generated.data[3]
data[0][4] => mux_pgc:auto_generated.data[4]
data[0][5] => mux_pgc:auto_generated.data[5]
data[0][6] => mux_pgc:auto_generated.data[6]
data[0][7] => mux_pgc:auto_generated.data[7]
data[0][8] => mux_pgc:auto_generated.data[8]
data[0][9] => mux_pgc:auto_generated.data[9]
data[0][10] => mux_pgc:auto_generated.data[10]
data[0][11] => mux_pgc:auto_generated.data[11]
data[0][12] => mux_pgc:auto_generated.data[12]
data[0][13] => mux_pgc:auto_generated.data[13]
data[0][14] => mux_pgc:auto_generated.data[14]
data[0][15] => mux_pgc:auto_generated.data[15]
data[1][0] => mux_pgc:auto_generated.data[16]
data[1][1] => mux_pgc:auto_generated.data[17]
data[1][2] => mux_pgc:auto_generated.data[18]
data[1][3] => mux_pgc:auto_generated.data[19]
data[1][4] => mux_pgc:auto_generated.data[20]
data[1][5] => mux_pgc:auto_generated.data[21]
data[1][6] => mux_pgc:auto_generated.data[22]
data[1][7] => mux_pgc:auto_generated.data[23]
data[1][8] => mux_pgc:auto_generated.data[24]
data[1][9] => mux_pgc:auto_generated.data[25]
data[1][10] => mux_pgc:auto_generated.data[26]
data[1][11] => mux_pgc:auto_generated.data[27]
data[1][12] => mux_pgc:auto_generated.data[28]
data[1][13] => mux_pgc:auto_generated.data[29]
data[1][14] => mux_pgc:auto_generated.data[30]
data[1][15] => mux_pgc:auto_generated.data[31]
sel[0] => mux_pgc:auto_generated.sel[0]
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= mux_pgc:auto_generated.result[0]
result[1] <= mux_pgc:auto_generated.result[1]
result[2] <= mux_pgc:auto_generated.result[2]
result[3] <= mux_pgc:auto_generated.result[3]
result[4] <= mux_pgc:auto_generated.result[4]
result[5] <= mux_pgc:auto_generated.result[5]
result[6] <= mux_pgc:auto_generated.result[6]
result[7] <= mux_pgc:auto_generated.result[7]
result[8] <= mux_pgc:auto_generated.result[8]
result[9] <= mux_pgc:auto_generated.result[9]
result[10] <= mux_pgc:auto_generated.result[10]
result[11] <= mux_pgc:auto_generated.result[11]
result[12] <= mux_pgc:auto_generated.result[12]
result[13] <= mux_pgc:auto_generated.result[13]
result[14] <= mux_pgc:auto_generated.result[14]
result[15] <= mux_pgc:auto_generated.result[15]


|mcu_sram_test|mux_sram:inst|lpm_mux:lpm_mux_component|mux_pgc:auto_generated
result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE
result[8] <= result_node[8].DB_MAX_OUTPUT_PORT_TYPE
result[9] <= result_node[9].DB_MAX_OUTPUT_PORT_TYPE
result[10] <= result_node[10].DB_MAX_OUTPUT_PORT_TYPE
result[11] <= result_node[11].DB_MAX_OUTPUT_PORT_TYPE
result[12] <= result_node[12].DB_MAX_OUTPUT_PORT_TYPE
result[13] <= result_node[13].DB_MAX_OUTPUT_PORT_TYPE
result[14] <= result_node[14].DB_MAX_OUTPUT_PORT_TYPE
result[15] <= result_node[15].DB_MAX_OUTPUT_PORT_TYPE


|mcu_sram_test|osc:inst2
da_wrx <= osc_display:inst3.da_wrx
rdclk => osc_display:inst3.clk
osc_dis_cs => osc_display:inst3.cs
oscsig => osc_control:inst.osc_sig
cs => osc_control:inst.cs
clk => osc_control:inst.clk
clk => osc_ram:inst2.clock
addrin[0] => osc_control:inst.oscaddrin[0]
addrin[1] => osc_control:inst.oscaddrin[1]
addrin[2] => osc_control:inst.oscaddrin[2]
addrin[3] => osc_control:inst.oscaddrin[3]
addrin[4] => osc_control:inst.oscaddrin[4]
addrin[5] => osc_control:inst.oscaddrin[5]
addrin[6] => osc_control:inst.oscaddrin[6]
addrin[7] => osc_control:inst.oscaddrin[7]
addrin[8] => osc_control:inst.oscaddrin[8]
addrin[9] => osc_control:inst.oscaddrin[9]
addrin[10] => osc_control:inst.oscaddrin[10]
addrin[11] => osc_control:inst.oscaddrin[11]
addrin[12] => osc_control:inst.oscaddrin[12]
addrin[13] => osc_control:inst.oscaddrin[13]
addrin[14] => osc_control:inst.oscaddrin[14]
addrin[15] => osc_control:inst.oscaddrin[15]
addrin[16] => osc_control:inst.oscaddrin[16]
datain[0] => osc_control:inst.oscdatain[0]
datain[1] => osc_control:inst.oscdatain[1]
datain[2] => osc_control:inst.oscdatain[2]
datain[3] => osc_control:inst.oscdatain[3]
datain[4] => osc_control:inst.oscdatain[4]
datain[5] => osc_control:inst.oscdatain[5]
datain[6] => osc_control:inst.oscdatain[6]
datain[7] => osc_control:inst.oscdatain[7]
datain[8] => osc_control:inst.oscdatain[8]
datain[9] => osc_control:inst.oscdatain[9]
datain[10] => osc_control:inst.oscdatain[10]
datain[11] => osc_control:inst.oscdatain[11]
datain[12] => osc_control:inst.oscdatain[12]
datain[13] => osc_control:inst.oscdatain[13]
datain[14] => osc_control:inst.oscdatain[14]
datain[15] => osc_control:inst.oscdatain[15]
da_wry <= osc_display:inst3.da_wry
x_da[0] <= osc_display:inst3.x_out[0]
x_da[1] <= osc_display:inst3.x_out[1]
x_da[2] <= osc_display:inst3.x_out[2]
x_da[3] <= osc_display:inst3.x_out[3]
x_da[4] <= osc_display:inst3.x_out[4]
x_da[5] <= osc_display:inst3.x_out[5]
x_da[6] <= osc_display:inst3.x_out[6]
x_da[7] <= osc_display:inst3.x_out[7]
y_da[0] <= osc_display:inst3.y_out[0]
y_da[1] <= osc_display:inst3.y_out[1]
y_da[2] <= osc_display:inst3.y_out[2]
y_da[3] <= osc_display:inst3.y_out[3]
y_da[4] <= osc_display:inst3.y_out[4]
y_da[5] <= osc_display:inst3.y_out[5]
y_da[6] <= osc_display:inst3.y_out[6]
y_da[7] <= osc_display:inst3.y_out[7]


|mcu_sram_test|osc:inst2|osc_display:inst3
clk => link_xout.CLK
clk => link_yout.CLK
clk => counttemp[12].CLK
clk => counttemp[11].CLK
clk => counttemp[10].CLK
clk => counttemp[9].CLK
clk => counttemp[8].CLK
clk => counttemp[7].CLK
clk => counttemp[6].CLK
clk => counttemp[5].CLK
clk => counttemp[4].CLK
clk => counttemp[3].CLK
clk => counttemp[2].CLK
clk => counttemp[1].CLK
clk => counttemp[0].CLK
clk => bittemp[2].CLK
clk => bittemp[1].CLK
clk => bittemp[0].CLK
clk => da_wrx~reg0.CLK
clk => da_wry~reg0.CLK
clk => RDADDR[9]~reg0.CLK
clk => RDADDR[8]~reg0.CLK
clk => RDADDR[7]~reg0.CLK
clk => RDADDR[6]~reg0.CLK
clk => RDADDR[5]~reg0.CLK
clk => RDADDR[4]~reg0.CLK
clk => RDADDR[3]~reg0.CLK
clk => RDADDR[2]~reg0.CLK
clk => RDADDR[1]~reg0.CLK
clk => RDADDR[0]~reg0.CLK
clk => xbuf[7].CLK
clk => xbuf[6].CLK
clk => xbuf[5].CLK
clk => xbuf[4].CLK
clk => xbuf[3].CLK
clk => xbuf[2].CLK
clk => xbuf[1].CLK
clk => xbuf[0].CLK
clk => ybuf[7].CLK
clk => ybuf[6].CLK
clk => ybuf[5].CLK
clk => ybuf[4].CLK
clk => ybuf[3].CLK
clk => ybuf[2].CLK
clk => ybuf[1].CLK
clk => ybuf[0].CLK
clk => state~8.IN1
cs => state~1.OUTPUTSELECT
cs => state~2.OUTPUTSELECT
cs => state~3.OUTPUTSELECT
cs => state~4.OUTPUTSELECT
cs => state~5.OUTPUTSELECT
cs => state~6.OUTPUTSELECT
cs => state~7.OUTPUTSELECT
cs => counttemp~26.OUTPUTSELECT
cs => counttemp~27.OUTPUTSELECT
cs => counttemp~28.OUTPUTSELECT
cs => counttemp~29.OUTPUTSELECT
cs => counttemp~30.OUTPUTSELECT
cs => counttemp~31.OUTPUTSELECT
cs => counttemp~32.OUTPUTSELECT
cs => counttemp~33.OUTPUTSELECT
cs => counttemp~34.OUTPUTSELECT
cs => counttemp~35.OUTPUTSELECT
cs => counttemp~36.OUTPUTSELECT
cs => counttemp~37.OUTPUTSELECT
cs => counttemp~38.OUTPUTSELECT
cs => bittemp~3.OUTPUTSELECT
cs => bittemp~4.OUTPUTSELECT
cs => bittemp~5.OUTPUTSELECT
cs => da_wrx~1.OUTPUTSELECT
cs => da_wry~0.OUTPUTSELECT
cs => link_yout.DATAIN
cs => link_xout.DATAIN
datain[0] => Mux0.IN7
datain[1] => Mux0.IN6
datain[2] => Mux0.IN5
datain[3] => Mux0.IN4
datain[4] => Mux0.IN3
datain[5] => Mux0.IN2
datain[6] => Mux0.IN1
datain[7] => Mux0.IN0
RDADDR[0] <= RDADDR[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RDADDR[1] <= RDADDR[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RDADDR[2] <= RDADDR[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RDADDR[3] <= RDADDR[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RDADDR[4] <= RDADDR[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RDADDR[5] <= RDADDR[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RDADDR[6] <= RDADDR[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RDADDR[7] <= RDADDR[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RDADDR[8] <= RDADDR[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RDADDR[9] <= RDADDR[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
x_out[0] <= x_out~7.DB_MAX_OUTPUT_PORT_TYPE
x_out[1] <= x_out~6.DB_MAX_OUTPUT_PORT_TYPE
x_out[2] <= x_out~5.DB_MAX_OUTPUT_PORT_TYPE
x_out[3] <= x_out~4.DB_MAX_OUTPUT_PORT_TYPE
x_out[4] <= x_out~3.DB_MAX_OUTPUT_PORT_TYPE
x_out[5] <= x_out~2.DB_MAX_OUTPUT_PORT_TYPE
x_out[6] <= x_out~1.DB_MAX_OUTPUT_PORT_TYPE
x_out[7] <= x_out~0.DB_MAX_OUTPUT_PORT_TYPE
y_out[0] <= y_out~7.DB_MAX_OUTPUT_PORT_TYPE
y_out[1] <= y_out~6.DB_MAX_OUTPUT_PORT_TYPE
y_out[2] <= y_out~5.DB_MAX_OUTPUT_PORT_TYPE
y_out[3] <= y_out~4.DB_MAX_OUTPUT_PORT_TYPE
y_out[4] <= y_out~3.DB_MAX_OUTPUT_PORT_TYPE
y_out[5] <= y_out~2.DB_MAX_OUTPUT_PORT_TYPE
y_out[6] <= y_out~1.DB_MAX_OUTPUT_PORT_TYPE
y_out[7] <= y_out~0.DB_MAX_OUTPUT_PORT_TYPE
da_wrx <= da_wrx~reg0.DB_MAX_OUTPUT_PORT_TYPE
da_wry <= da_wry~reg0.DB_MAX_OUTPUT_PORT_TYPE


|mcu_sram_test|osc:inst2|osc_ram:inst2
clock => clock~0.IN1
data[0] => data[0]~7.IN1
data[1] => data[1]~6.IN1
data[2] => data[2]~5.IN1
data[3] => data[3]~4.IN1
data[4] => data[4]~3.IN1
data[5] => data[5]~2.IN1
data[6] => data[6]~1.IN1
data[7] => data[7]~0.IN1
rdaddress[0] => rdaddress[0]~9.IN1
rdaddress[1] => rdaddress[1]~8.IN1
rdaddress[2] => rdaddress[2]~7.IN1
rdaddress[3] => rdaddress[3]~6.IN1
rdaddress[4] => rdaddress[4]~5.IN1
rdaddress[5] => rdaddress[5]~4.IN1
rdaddress[6] => rdaddress[6]~3.IN1
rdaddress[7] => rdaddress[7]~2.IN1
rdaddress[8] => rdaddress[8]~1.IN1
rdaddress[9] => rdaddress[9]~0.IN1
rden => rden~0.IN1
wraddress[0] => wraddress[0]~9.IN1
wraddress[1] => wraddress[1]~8.IN1
wraddress[2] => wraddress[2]~7.IN1
wraddress[3] => wraddress[3]~6.IN1
wraddress[4] => wraddress[4]~5.IN1
wraddress[5] => wraddress[5]~4.IN1
wraddress[6] => wraddress[6]~3.IN1
wraddress[7] => wraddress[7]~2.IN1
wraddress[8] => wraddress[8]~1.IN1
wraddress[9] => wraddress[9]~0.IN1
wren => wren~0.IN1
q[0] <= altsyncram:altsyncram_component.q_b
q[1] <= altsyncram:altsyncram_component.q_b
q[2] <= altsyncram:altsyncram_component.q_b
q[3] <= altsyncram:altsyncram_component.q_b
q[4] <= altsyncram:altsyncram_component.q_b
q[5] <= altsyncram:altsyncram_component.q_b
q[6] <= altsyncram:altsyncram_component.q_b
q[7] <= altsyncram:altsyncram_component.q_b


|mcu_sram_test|osc:inst2|osc_ram:inst2|altsyncram:altsyncram_component
wren_a => altsyncram_usp1:auto_generated.wren_a
wren_b => ~NO_FANOUT~
rden_b => altsyncram_usp1:auto_generated.rden_b
data_a[0] => altsyncram_usp1:auto_generated.data_a[0]
data_a[1] => altsyncram_usp1:auto_generated.data_a[1]
data_a[2] => altsyncram_usp1:auto_generated.data_a[2]
data_a[3] => altsyncram_usp1:auto_generated.data_a[3]
data_a[4] => altsyncram_usp1:auto_generated.data_a[4]
data_a[5] => altsyncram_usp1:auto_generated.data_a[5]
data_a[6] => altsyncram_usp1:auto_generated.data_a[6]
data_a[7] => altsyncram_usp1:auto_generated.data_a[7]
data_b[0] => ~NO_FANOUT~
data_b[1] => ~NO_FANOUT~
data_b[2] => ~NO_FANOUT~
data_b[3] => ~NO_FANOUT~
data_b[4] => ~NO_FANOUT~
data_b[5] => ~NO_FANOUT~
data_b[6] => ~NO_FANOUT~
data_b[7] => ~NO_FANOUT~
address_a[0] => altsyncram_usp1:auto_generated.address_a[0]
address_a[1] => altsyncram_usp1:auto_generated.address_a[1]
address_a[2] => altsyncram_usp1:auto_generated.address_a[2]
address_a[3] => altsyncram_usp1:auto_generated.address_a[3]