mcu_sram_test.tan.qmsg

verilog编写基于FPGA的示波器核心实现

{ "Info" "ITDB_TH_RESULT" "osc:inst2\|osc_display:inst3\|bittemp\[1\] csdis clk -2.257 ns register " "Info: th for register \"osc:inst2\|osc_display:inst3\|bittemp\[1\]\" (data pin = \"csdis\", clock pin = \"clk\") is -2.257 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.369 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.369 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 200 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 200; CLK Node = 'clk'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mcu_sram_test.bdf" "" { Schematic "F:/fpga test/fpge示波器/mcu_sram beta1.1/mcu_sram_test.bdf" { { -448 -112 56 -432 "clk" "" } { 136 -112 -72 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns mfreq:freq8\|count\[2\] 2 REG LC_X8_Y10_N4 49 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N4; Fanout = 49; REG Node = 'mfreq:freq8\|count\[2\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.680 ns" { clk mfreq:freq8|count[2] } "NODE_NAME" } } { "mfreq.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/mfreq.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.509 ns) + CELL(0.711 ns) 7.369 ns osc:inst2\|osc_display:inst3\|bittemp\[1\] 3 REG LC_X16_Y11_N5 3 " "Info: 3: + IC(3.509 ns) + CELL(0.711 ns) = 7.369 ns; Loc. = LC_X16_Y11_N5; Fanout = 3; REG Node = 'osc:inst2\|osc_display:inst3\|bittemp\[1\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.220 ns" { mfreq:freq8|count[2] osc:inst2|osc_display:inst3|bittemp[1] } "NODE_NAME" } } { "osc_display.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc_display.v" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.27 % ) " "Info: Total cell delay = 3.115 ns ( 42.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.254 ns ( 57.73 % ) " "Info: Total interconnect delay = 4.254 ns ( 57.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.369 ns" { clk mfreq:freq8|count[2] osc:inst2|osc_display:inst3|bittemp[1] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "7.369 ns" { clk clk~out0 mfreq:freq8|count[2] osc:inst2|osc_display:inst3|bittemp[1] } { 0.000ns 0.000ns 0.745ns 3.509ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "osc_display.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc_display.v" 115 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.641 ns - Shortest pin register " "Info: - Shortest pin to register delay is 9.641 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns csdis 1 PIN PIN_126 15 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_126; Fanout = 15; PIN Node = 'csdis'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { csdis } "NODE_NAME" } } { "mcu_sram_test.bdf" "" { Schematic "F:/fpga test/fpge示波器/mcu_sram beta1.1/mcu_sram_test.bdf" { { -200 -184 -16 -184 "csdis" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.863 ns) + CELL(0.309 ns) 9.641 ns osc:inst2\|osc_display:inst3\|bittemp\[1\] 2 REG LC_X16_Y11_N5 3 " "Info: 2: + IC(7.863 ns) + CELL(0.309 ns) = 9.641 ns; Loc. = LC_X16_Y11_N5; Fanout = 3; REG Node = 'osc:inst2\|osc_display:inst3\|bittemp\[1\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.172 ns" { csdis osc:inst2|osc_display:inst3|bittemp[1] } "NODE_NAME" } } { "osc_display.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc_display.v" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.778 ns ( 18.44 % ) " "Info: Total cell delay = 1.778 ns ( 18.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.863 ns ( 81.56 % ) " "Info: Total interconnect delay = 7.863 ns ( 81.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.641 ns" { csdis osc:inst2|osc_display:inst3|bittemp[1] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "9.641 ns" { csdis csdis~out0 osc:inst2|osc_display:inst3|bittemp[1] } { 0.000ns 0.000ns 7.863ns } { 0.000ns 1.469ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.369 ns" { clk mfreq:freq8|count[2] osc:inst2|osc_display:inst3|bittemp[1] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "7.369 ns" { clk clk~out0 mfreq:freq8|count[2] osc:inst2|osc_display:inst3|bittemp[1] } { 0.000ns 0.000ns 0.745ns 3.509ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.641 ns" { csdis osc:inst2|osc_display:inst3|bittemp[1] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "9.641 ns" { csdis csdis~out0 osc:inst2|osc_display:inst3|bittemp[1] } { 0.000ns 0.000ns 7.863ns } { 0.000ns 1.469ns 0.309ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 4 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 18 15:03:43 2007 " "Info: Processing ended: Wed Jul 18 15:03:43 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}