mcu_sram_test.tan.qmsg

verilog编写基于FPGA的示波器核心实现

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "osc:inst2\|osc_ram:inst2\|altsyncram:altsyncram_component\|altsyncram_usp1:auto_generated\|q_b\[2\] osc:inst2\|osc_display:inst3\|ybuf\[2\] clk 1.285 ns " "Info: Found hold time violation between source  pin or register \"osc:inst2\|osc_ram:inst2\|altsyncram:altsyncram_component\|altsyncram_usp1:auto_generated\|q_b\[2\]\" and destination pin or register \"osc:inst2\|osc_display:inst3\|ybuf\[2\]\" for clock \"clk\" (Hold time is 1.285 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.435 ns + Largest " "Info: + Largest clock skew is 4.435 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.369 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.369 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 200 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 200; CLK Node = 'clk'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mcu_sram_test.bdf" "" { Schematic "F:/fpga test/fpge示波器/mcu_sram beta1.1/mcu_sram_test.bdf" { { -448 -112 56 -432 "clk" "" } { 136 -112 -72 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns mfreq:freq8\|count\[2\] 2 REG LC_X8_Y10_N4 49 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N4; Fanout = 49; REG Node = 'mfreq:freq8\|count\[2\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.680 ns" { clk mfreq:freq8|count[2] } "NODE_NAME" } } { "mfreq.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/mfreq.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.509 ns) + CELL(0.711 ns) 7.369 ns osc:inst2\|osc_display:inst3\|ybuf\[2\] 3 REG LC_X16_Y11_N9 1 " "Info: 3: + IC(3.509 ns) + CELL(0.711 ns) = 7.369 ns; Loc. = LC_X16_Y11_N9; Fanout = 1; REG Node = 'osc:inst2\|osc_display:inst3\|ybuf\[2\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.220 ns" { mfreq:freq8|count[2] osc:inst2|osc_display:inst3|ybuf[2] } "NODE_NAME" } } { "osc_display.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc_display.v" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.27 % ) " "Info: Total cell delay = 3.115 ns ( 42.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.254 ns ( 57.73 % ) " "Info: Total interconnect delay = 4.254 ns ( 57.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.369 ns" { clk mfreq:freq8|count[2] osc:inst2|osc_display:inst3|ybuf[2] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "7.369 ns" { clk clk~out0 mfreq:freq8|count[2] osc:inst2|osc_display:inst3|ybuf[2] } { 0.000ns 0.000ns 0.745ns 3.509ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.934 ns - Shortest memory " "Info: - Shortest clock path from clock \"clk\" to source memory is 2.934 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 200 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 200; CLK Node = 'clk'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mcu_sram_test.bdf" "" { Schematic "F:/fpga test/fpge示波器/mcu_sram beta1.1/mcu_sram_test.bdf" { { -448 -112 56 -432 "clk" "" } { 136 -112 -72 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.703 ns) 2.934 ns osc:inst2\|osc_ram:inst2\|altsyncram:altsyncram_component\|altsyncram_usp1:auto_generated\|q_b\[2\] 2 MEM M4K_X17_Y10 1 " "Info: 2: + IC(0.762 ns) + CELL(0.703 ns) = 2.934 ns; Loc. = M4K_X17_Y10; Fanout = 1; MEM Node = 'osc:inst2\|osc_ram:inst2\|altsyncram:altsyncram_component\|altsyncram_usp1:auto_generated\|q_b\[2\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.465 ns" { clk osc:inst2|osc_ram:inst2|altsyncram:altsyncram_component|altsyncram_usp1:auto_generated|q_b[2] } "NODE_NAME" } } { "db/altsyncram_usp1.tdf" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/db/altsyncram_usp1.tdf" 42 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.172 ns ( 74.03 % ) " "Info: Total cell delay = 2.172 ns ( 74.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.97 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.934 ns" { clk osc:inst2|osc_ram:inst2|altsyncram:altsyncram_component|altsyncram_usp1:auto_generated|q_b[2] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.934 ns" { clk clk~out0 osc:inst2|osc_ram:inst2|altsyncram:altsyncram_component|altsyncram_usp1:auto_generated|q_b[2] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.703ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.369 ns" { clk mfreq:freq8|count[2] osc:inst2|osc_display:inst3|ybuf[2] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "7.369 ns" { clk clk~out0 mfreq:freq8|count[2] osc:inst2|osc_display:inst3|ybuf[2] } { 0.000ns 0.000ns 0.745ns 3.509ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.934 ns" { clk osc:inst2|osc_ram:inst2|altsyncram:altsyncram_component|altsyncram_usp1:auto_generated|q_b[2] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.934 ns" { clk clk~out0 osc:inst2|osc_ram:inst2|altsyncram:altsyncram_component|altsyncram_usp1:auto_generated|q_b[2] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.703ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns - " "Info: - Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_usp1.tdf" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/db/altsyncram_usp1.tdf" 42 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.515 ns - Shortest memory register " "Info: - Shortest memory to register delay is 2.515 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.104 ns) 0.104 ns osc:inst2\|osc_ram:inst2\|altsyncram:altsyncram_component\|altsyncram_usp1:auto_generated\|q_b\[2\] 1 MEM M4K_X17_Y10 1 " "Info: 1: + IC(0.000 ns) + CELL(0.104 ns) = 0.104 ns; Loc. = M4K_X17_Y10; Fanout = 1; MEM Node = 'osc:inst2\|osc_ram:inst2\|altsyncram:altsyncram_component\|altsyncram_usp1:auto_generated\|q_b\[2\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { osc:inst2|osc_ram:inst2|altsyncram:altsyncram_component|altsyncram_usp1:auto_generated|q_b[2] } "NODE_NAME" } } { "db/altsyncram_usp1.tdf" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/db/altsyncram_usp1.tdf" 42 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.363 ns) + CELL(0.114 ns) 1.581 ns osc:inst2\|osc_display:inst3\|Mux0~32 2 COMB LC_X16_Y11_N4 14 " "Info: 2: + IC(1.363 ns) + CELL(0.114 ns) = 1.581 ns; Loc. = LC_X16_Y11_N4; Fanout = 14; COMB Node = 'osc:inst2\|osc_display:inst3\|Mux0~32'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.477 ns" { osc:inst2|osc_ram:inst2|altsyncram:altsyncram_component|altsyncram_usp1:auto_generated|q_b[2] osc:inst2|osc_display:inst3|Mux0~32 } "NODE_NAME" } } { "osc_display.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc_display.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.456 ns) + CELL(0.478 ns) 2.515 ns osc:inst2\|osc_display:inst3\|ybuf\[2\] 3 REG LC_X16_Y11_N9 1 " "Info: 3: + IC(0.456 ns) + CELL(0.478 ns) = 2.515 ns; Loc. = LC_X16_Y11_N9; Fanout = 1; REG Node = 'osc:inst2\|osc_display:inst3\|ybuf\[2\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.934 ns" { osc:inst2|osc_display:inst3|Mux0~32 osc:inst2|osc_display:inst3|ybuf[2] } "NODE_NAME" } } { "osc_display.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc_display.v" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.696 ns ( 27.67 % ) " "Info: Total cell delay = 0.696 ns ( 27.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.819 ns ( 72.33 % ) " "Info: Total interconnect delay = 1.819 ns ( 72.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.515 ns" { osc:inst2|osc_ram:inst2|altsyncram:altsyncram_component|altsyncram_usp1:auto_generated|q_b[2] osc:inst2|osc_display:inst3|Mux0~32 osc:inst2|osc_display:inst3|ybuf[2] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.515 ns" { osc:inst2|osc_ram:inst2|altsyncram:altsyncram_component|altsyncram_usp1:auto_generated|q_b[2] osc:inst2|osc_display:inst3|Mux0~32 osc:inst2|osc_display:inst3|ybuf[2] } { 0.000ns 1.363ns 0.456ns } { 0.104ns 0.114ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "osc_display.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc_display.v" 115 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.369 ns" { clk mfreq:freq8|count[2] osc:inst2|osc_display:inst3|ybuf[2] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "7.369 ns" { clk clk~out0 mfreq:freq8|count[2] osc:inst2|osc_display:inst3|ybuf[2] } { 0.000ns 0.000ns 0.745ns 3.509ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.934 ns" { clk osc:inst2|osc_ram:inst2|altsyncram:altsyncram_component|altsyncram_usp1:auto_generated|q_b[2] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.934 ns" { clk clk~out0 osc:inst2|osc_ram:inst2|altsyncram:altsyncram_component|altsyncram_usp1:auto_generated|q_b[2] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.703ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.515 ns" { osc:inst2|osc_ram:inst2|altsyncram:altsyncram_component|altsyncram_usp1:auto_generated|q_b[2] osc:inst2|osc_display:inst3|Mux0~32 osc:inst2|osc_display:inst3|ybuf[2] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.515 ns" { osc:inst2|osc_ram:inst2|altsyncram:altsyncram_component|altsyncram_usp1:auto_generated|q_b[2] osc:inst2|osc_display:inst3|Mux0~32 osc:inst2|osc_display:inst3|ybuf[2] } { 0.000ns 1.363ns 0.456ns } { 0.104ns 0.114ns 0.478ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "sram_control:inst4\|addrbuf\[7\] cssram clk 9.462 ns register " "Info: tsu for register \"sram_control:inst4\|addrbuf\[7\]\" (data pin = \"cssram\", clock pin = \"clk\") is 9.462 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.334 ns + Longest pin register " "Info: + Longest pin to register delay is 12.334 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns cssram 1 PIN PIN_127 51 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_127; Fanout = 51; PIN Node = 'cssram'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cssram } "NODE_NAME" } } { "mcu_sram_test.bdf" "" { Schematic "F:/fpga test/fpge示波器/mcu_sram beta1.1/mcu_sram_test.bdf" { { -320 -184 -16 -304 "cssram" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.216 ns) + CELL(0.590 ns) 9.275 ns sram_control:inst4\|addrbuf\[1\]~1097 2 COMB LC_X25_Y6_N4 17 " "Info: 2: + IC(7.216 ns) + CELL(0.590 ns) = 9.275 ns; Loc. = LC_X25_Y6_N4; Fanout = 17; COMB Node = 'sram_control:inst4\|addrbuf\[1\]~1097'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.806 ns" { cssram sram_control:inst4|addrbuf[1]~1097 } "NODE_NAME" } } { "sram_control.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/sram_control.v" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.947 ns) + CELL(1.112 ns) 12.334 ns sram_control:inst4\|addrbuf\[7\] 3 REG LC_X19_Y8_N9 3 " "Info: 3: + IC(1.947 ns) + CELL(1.112 ns) = 12.334 ns; Loc. = LC_X19_Y8_N9; Fanout = 3; REG Node = 'sram_control:inst4\|addrbuf\[7\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.059 ns" { sram_control:inst4|addrbuf[1]~1097 sram_control:inst4|addrbuf[7] } "NODE_NAME" } } { "sram_control.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/sram_control.v" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.171 ns ( 25.71 % ) " "Info: Total cell delay = 3.171 ns ( 25.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.163 ns ( 74.29 % ) " "Info: Total interconnect delay = 9.163 ns ( 74.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.334 ns" { cssram sram_control:inst4|addrbuf[1]~1097 sram_control:inst4|addrbuf[7] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "12.334 ns" { cssram cssram~out0 sram_control:inst4|addrbuf[1]~1097 sram_control:inst4|addrbuf[7] } { 0.000ns 0.000ns 7.216ns 1.947ns } { 0.000ns 1.469ns 0.590ns 1.112ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "sram_control.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/sram_control.v" 76 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.909 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.909 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 200 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 200; CLK Node = 'clk'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mcu_sram_test.bdf" "" { Schematic "F:/fpga test/fpge示波器/mcu_sram beta1.1/mcu_sram_test.bdf" { { -448 -112 56 -432 "clk" "" } { 136 -112 -72 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.729 ns) + CELL(0.711 ns) 2.909 ns sram_control:inst4\|addrbuf\[7\] 2 REG LC_X19_Y8_N9 3 " "Info: 2: + IC(0.729 ns) + CELL(0.711 ns) = 2.909 ns; Loc. = LC_X19_Y8_N9; Fanout = 3; REG Node = 'sram_control:inst4\|addrbuf\[7\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.440 ns" { clk sram_control:inst4|addrbuf[7] } "NODE_NAME" } } { "sram_control.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/sram_control.v" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.94 % ) " "Info: Total cell delay = 2.180 ns ( 74.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.729 ns ( 25.06 % ) " "Info: Total interconnect delay = 0.729 ns ( 25.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.909 ns" { clk sram_control:inst4|addrbuf[7] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.909 ns" { clk clk~out0 sram_control:inst4|addrbuf[7] } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.334 ns" { cssram sram_control:inst4|addrbuf[1]~1097 sram_control:inst4|addrbuf[7] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "12.334 ns" { cssram cssram~out0 sram_control:inst4|addrbuf[1]~1097 sram_control:inst4|addrbuf[7] } { 0.000ns 0.000ns 7.216ns 1.947ns } { 0.000ns 1.469ns 0.590ns 1.112ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.909 ns" { clk sram_control:inst4|addrbuf[7] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.909 ns" { clk clk~out0 sram_control:inst4|addrbuf[7] } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk y_da\[1\] osc:inst2\|osc_display:inst3\|link_xout 14.406 ns register " "Info: tco from clock \"clk\" to destination pin \"y_da\[1\]\" through register \"osc:inst2\|osc_display:inst3\|link_xout\" is 14.406 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.399 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.399 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 200 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 200; CLK Node = 'clk'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mcu_sram_test.bdf" "" { Schematic "F:/fpga test/fpge示波器/mcu_sram beta1.1/mcu_sram_test.bdf" { { -448 -112 56 -432 "clk" "" } { 136 -112 -72 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns mfreq:freq8\|count\[2\] 2 REG LC_X8_Y10_N4 49 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N4; Fanout = 49; REG Node = 'mfreq:freq8\|count\[2\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.680 ns" { clk mfreq:freq8|count[2] } "NODE_NAME" } } { "mfreq.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/mfreq.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.539 ns) + CELL(0.711 ns) 7.399 ns osc:inst2\|osc_display:inst3\|link_xout 3 REG LC_X16_Y14_N2 16 " "Info: 3: + IC(3.539 ns) + CELL(0.711 ns) = 7.399 ns; Loc. = LC_X16_Y14_N2; Fanout = 16; REG Node = 'osc:inst2\|osc_display:inst3\|link_xout'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.250 ns" { mfreq:freq8|count[2] osc:inst2|osc_display:inst3|link_xout } "NODE_NAME" } } { "osc_display.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc_display.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.10 % ) " "Info: Total cell delay = 3.115 ns ( 42.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.284 ns ( 57.90 % ) " "Info: Total interconnect delay = 4.284 ns ( 57.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.399 ns" { clk mfreq:freq8|count[2] osc:inst2|osc_display:inst3|link_xout } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "7.399 ns" { clk clk~out0 mfreq:freq8|count[2] osc:inst2|osc_display:inst3|link_xout } { 0.000ns 0.000ns 0.745ns 3.539ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "osc_display.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc_display.v" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.783 ns + Longest register pin " "Info: + Longest register to pin delay is 6.783 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns osc:inst2\|osc_display:inst3\|link_xout 1 REG LC_X16_Y14_N2 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y14_N2; Fanout = 16; REG Node = 'osc:inst2\|osc_display:inst3\|link_xout'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { osc:inst2|osc_display:inst3|link_xout } "NODE_NAME" } } { "osc_display.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc_display.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.704 ns) + CELL(2.079 ns) 6.783 ns y_da\[1\] 2 PIN PIN_226 0 " "Info: 2: + IC(4.704 ns) + CELL(2.079 ns) = 6.783 ns; Loc. = PIN_226; Fanout = 0; PIN Node = 'y_da\[1\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.783 ns" { osc:inst2|osc_display:inst3|link_xout y_da[1] } "NODE_NAME" } } { "mcu_sram_test.bdf" "" { Schematic "F:/fpga test/fpge示波器/mcu_sram beta1.1/mcu_sram_test.bdf" { { 64 424 600 80 "y_da\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.079 ns ( 30.65 % ) " "Info: Total cell delay = 2.079 ns ( 30.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.704 ns ( 69.35 % ) " "Info: Total interconnect delay = 4.704 ns ( 69.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.783 ns" { osc:inst2|osc_display:inst3|link_xout y_da[1] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "6.783 ns" { osc:inst2|osc_display:inst3|link_xout y_da[1] } { 0.000ns 4.704ns } { 0.000ns 2.079ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.399 ns" { clk mfreq:freq8|count[2] osc:inst2|osc_display:inst3|link_xout } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "7.399 ns" { clk clk~out0 mfreq:freq8|count[2] osc:inst2|osc_display:inst3|link_xout } { 0.000ns 0.000ns 0.745ns 3.539ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.783 ns" { osc:inst2|osc_display:inst3|link_xout y_da[1] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "6.783 ns" { osc:inst2|osc_display:inst3|link_xout y_da[1] } { 0.000ns 4.704ns } { 0.000ns 2.079ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "sramdata\[0\] mcudata\[0\] 13.856 ns Longest " "Info: Longest tpd from source pin \"sramdata\[0\]\" to destination pin \"mcudata\[0\]\" is 13.856 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sramdata\[0\] 1 PIN PIN_88 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_88; Fanout = 1; PIN Node = 'sramdata\[0\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sramdata[0] } "NODE_NAME" } } { "mcu_sram_test.bdf" "" { Schematic "F:/fpga test/fpge示波器/mcu_sram beta1.1/mcu_sram_test.bdf" { { -416 800 976 -400 "sramdata\[15..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns sramdata~15 2 COMB IOC_X16_Y0_N0 1 " "Info: 2: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = IOC_X16_Y0_N0; Fanout = 1; COMB Node = 'sramdata~15'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.475 ns" { sramdata[0] sramdata~15 } "NODE_NAME" } } { "mcu_sram_test.bdf" "" { Schematic "F:/fpga test/fpge示波器/mcu_sram beta1.1/mcu_sram_test.bdf" { { -416 800 976 -400 "sramdata\[15..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.102 ns) + CELL(0.442 ns) 8.019 ns mcu_fpga_control:inst8\|databus~510 3 COMB LC_X26_Y1_N9 1 " "Info: 3: + IC(6.102 ns) + CELL(0.442 ns) = 8.019 ns; Loc. = LC_X26_Y1_N9; Fanout = 1; COMB Node = 'mcu_fpga_control:inst8\|databus~510'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.544 ns" { sramdata~15 mcu_fpga_control:inst8|databus~510 } "NODE_NAME" } } { "mcu_fpga_control.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/mcu_fpga_control.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.729 ns) + CELL(2.108 ns) 13.856 ns mcudata\[0\] 4 PIN PIN_202 0 " "Info: 4: + IC(3.729 ns) + CELL(2.108 ns) = 13.856 ns; Loc. = PIN_202; Fanout = 0; PIN Node = 'mcudata\[0\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.837 ns" { mcu_fpga_control:inst8|databus~510 mcudata[0] } "NODE_NAME" } } { "mcu_sram_test.bdf" "" { Schematic "F:/fpga test/fpge示波器/mcu_sram beta1.1/mcu_sram_test.bdf" { { -504 -120 56 -488 "mcudata\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.025 ns ( 29.05 % ) " "Info: Total cell delay = 4.025 ns ( 29.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.831 ns ( 70.95 % ) " "Info: Total interconnect delay = 9.831 ns ( 70.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "13.856 ns" { sramdata[0] sramdata~15 mcu_fpga_control:inst8|databus~510 mcudata[0] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "13.856 ns" { sramdata[0] sramdata~15 mcu_fpga_control:inst8|databus~510 mcudata[0] } { 0.000ns 0.000ns 6.102ns 3.729ns } { 0.000ns 1.475ns 0.442ns 2.108ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}