mcu_sram_test.tan.qmsg

verilog编写基于FPGA的示波器核心实现

{ "Warning" "WTAN_CLOCK_SETTING_NOT_USED" "clk " "Warning: Clock Setting \"clk\" is unassigned" {  } {  } 0 0 "Clock Setting \"%1!s!\" is unassigned" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "mfreq:freq8\|count\[2\] " "Info: Detected ripple clock \"mfreq:freq8\|count\[2\]\" as buffer" {  } { { "mfreq.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/mfreq.v" 18 -1 0 } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "mfreq:freq8\|count\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register osc:inst2\|osc_display:inst3\|RDADDR\[5\] memory osc:inst2\|osc_ram:inst2\|altsyncram:altsyncram_component\|altsyncram_usp1:auto_generated\|ram_block1a6~portb_address_reg5 141.66 MHz 7.059 ns Internal " "Info: Clock \"clk\" has Internal fmax of 141.66 MHz between source register \"osc:inst2\|osc_display:inst3\|RDADDR\[5\]\" and destination memory \"osc:inst2\|osc_ram:inst2\|altsyncram:altsyncram_component\|altsyncram_usp1:auto_generated\|ram_block1a6~portb_address_reg5\" (period= 7.059 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.289 ns + Longest register memory " "Info: + Longest register to memory delay is 2.289 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns osc:inst2\|osc_display:inst3\|RDADDR\[5\] 1 REG LC_X16_Y10_N1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y10_N1; Fanout = 2; REG Node = 'osc:inst2\|osc_display:inst3\|RDADDR\[5\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { osc:inst2|osc_display:inst3|RDADDR[5] } "NODE_NAME" } } { "osc_display.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc_display.v" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.959 ns) + CELL(0.330 ns) 2.289 ns osc:inst2\|osc_ram:inst2\|altsyncram:altsyncram_component\|altsyncram_usp1:auto_generated\|ram_block1a6~portb_address_reg5 2 MEM M4K_X17_Y9 4 " "Info: 2: + IC(1.959 ns) + CELL(0.330 ns) = 2.289 ns; Loc. = M4K_X17_Y9; Fanout = 4; MEM Node = 'osc:inst2\|osc_ram:inst2\|altsyncram:altsyncram_component\|altsyncram_usp1:auto_generated\|ram_block1a6~portb_address_reg5'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.289 ns" { osc:inst2|osc_display:inst3|RDADDR[5] osc:inst2|osc_ram:inst2|altsyncram:altsyncram_component|altsyncram_usp1:auto_generated|ram_block1a6~portb_address_reg5 } "NODE_NAME" } } { "db/altsyncram_usp1.tdf" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/db/altsyncram_usp1.tdf" 239 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.330 ns ( 14.42 % ) " "Info: Total cell delay = 0.330 ns ( 14.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.959 ns ( 85.58 % ) " "Info: Total interconnect delay = 1.959 ns ( 85.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.289 ns" { osc:inst2|osc_display:inst3|RDADDR[5] osc:inst2|osc_ram:inst2|altsyncram:altsyncram_component|altsyncram_usp1:auto_generated|ram_block1a6~portb_address_reg5 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.289 ns" { osc:inst2|osc_display:inst3|RDADDR[5] osc:inst2|osc_ram:inst2|altsyncram:altsyncram_component|altsyncram_usp1:auto_generated|ram_block1a6~portb_address_reg5 } { 0.000ns 1.959ns } { 0.000ns 0.330ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.453 ns - Smallest " "Info: - Smallest clock skew is -4.453 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.916 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk\" to destination memory is 2.916 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 200 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 200; CLK Node = 'clk'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mcu_sram_test.bdf" "" { Schematic "F:/fpga test/fpge示波器/mcu_sram beta1.1/mcu_sram_test.bdf" { { -448 -112 56 -432 "clk" "" } { 136 -112 -72 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.729 ns) + CELL(0.718 ns) 2.916 ns osc:inst2\|osc_ram:inst2\|altsyncram:altsyncram_component\|altsyncram_usp1:auto_generated\|ram_block1a6~portb_address_reg5 2 MEM M4K_X17_Y9 4 " "Info: 2: + IC(0.729 ns) + CELL(0.718 ns) = 2.916 ns; Loc. = M4K_X17_Y9; Fanout = 4; MEM Node = 'osc:inst2\|osc_ram:inst2\|altsyncram:altsyncram_component\|altsyncram_usp1:auto_generated\|ram_block1a6~portb_address_reg5'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.447 ns" { clk osc:inst2|osc_ram:inst2|altsyncram:altsyncram_component|altsyncram_usp1:auto_generated|ram_block1a6~portb_address_reg5 } "NODE_NAME" } } { "db/altsyncram_usp1.tdf" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/db/altsyncram_usp1.tdf" 239 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.187 ns ( 75.00 % ) " "Info: Total cell delay = 2.187 ns ( 75.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.729 ns ( 25.00 % ) " "Info: Total interconnect delay = 0.729 ns ( 25.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.916 ns" { clk osc:inst2|osc_ram:inst2|altsyncram:altsyncram_component|altsyncram_usp1:auto_generated|ram_block1a6~portb_address_reg5 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.916 ns" { clk clk~out0 osc:inst2|osc_ram:inst2|altsyncram:altsyncram_component|altsyncram_usp1:auto_generated|ram_block1a6~portb_address_reg5 } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.718ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.369 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.369 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 200 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 200; CLK Node = 'clk'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mcu_sram_test.bdf" "" { Schematic "F:/fpga test/fpge示波器/mcu_sram beta1.1/mcu_sram_test.bdf" { { -448 -112 56 -432 "clk" "" } { 136 -112 -72 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns mfreq:freq8\|count\[2\] 2 REG LC_X8_Y10_N4 49 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N4; Fanout = 49; REG Node = 'mfreq:freq8\|count\[2\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.680 ns" { clk mfreq:freq8|count[2] } "NODE_NAME" } } { "mfreq.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/mfreq.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.509 ns) + CELL(0.711 ns) 7.369 ns osc:inst2\|osc_display:inst3\|RDADDR\[5\] 3 REG LC_X16_Y10_N1 2 " "Info: 3: + IC(3.509 ns) + CELL(0.711 ns) = 7.369 ns; Loc. = LC_X16_Y10_N1; Fanout = 2; REG Node = 'osc:inst2\|osc_display:inst3\|RDADDR\[5\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.220 ns" { mfreq:freq8|count[2] osc:inst2|osc_display:inst3|RDADDR[5] } "NODE_NAME" } } { "osc_display.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc_display.v" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.27 % ) " "Info: Total cell delay = 3.115 ns ( 42.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.254 ns ( 57.73 % ) " "Info: Total interconnect delay = 4.254 ns ( 57.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.369 ns" { clk mfreq:freq8|count[2] osc:inst2|osc_display:inst3|RDADDR[5] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "7.369 ns" { clk clk~out0 mfreq:freq8|count[2] osc:inst2|osc_display:inst3|RDADDR[5] } { 0.000ns 0.000ns 0.745ns 3.509ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.916 ns" { clk osc:inst2|osc_ram:inst2|altsyncram:altsyncram_component|altsyncram_usp1:auto_generated|ram_block1a6~portb_address_reg5 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.916 ns" { clk clk~out0 osc:inst2|osc_ram:inst2|altsyncram:altsyncram_component|altsyncram_usp1:auto_generated|ram_block1a6~portb_address_reg5 } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.718ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.369 ns" { clk mfreq:freq8|count[2] osc:inst2|osc_display:inst3|RDADDR[5] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "7.369 ns" { clk clk~out0 mfreq:freq8|count[2] osc:inst2|osc_display:inst3|RDADDR[5] } { 0.000ns 0.000ns 0.745ns 3.509ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "osc_display.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/osc_display.v" 115 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_usp1.tdf" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/db/altsyncram_usp1.tdf" 239 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.289 ns" { osc:inst2|osc_display:inst3|RDADDR[5] osc:inst2|osc_ram:inst2|altsyncram:altsyncram_component|altsyncram_usp1:auto_generated|ram_block1a6~portb_address_reg5 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.289 ns" { osc:inst2|osc_display:inst3|RDADDR[5] osc:inst2|osc_ram:inst2|altsyncram:altsyncram_component|altsyncram_usp1:auto_generated|ram_block1a6~portb_address_reg5 } { 0.000ns 1.959ns } { 0.000ns 0.330ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.916 ns" { clk osc:inst2|osc_ram:inst2|altsyncram:altsyncram_component|altsyncram_usp1:auto_generated|ram_block1a6~portb_address_reg5 } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "2.916 ns" { clk clk~out0 osc:inst2|osc_ram:inst2|altsyncram:altsyncram_component|altsyncram_usp1:auto_generated|ram_block1a6~portb_address_reg5 } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.718ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.369 ns" { clk mfreq:freq8|count[2] osc:inst2|osc_display:inst3|RDADDR[5] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "7.369 ns" { clk clk~out0 mfreq:freq8|count[2] osc:inst2|osc_display:inst3|RDADDR[5] } { 0.000ns 0.000ns 0.745ns 3.509ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 41 " "Warning: Circuit may not operate. Detected 41 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}