dds.hier_info

verilog编写基于fpga的DDS实现

|dds
output[0] <= mux4:inst3.result[0]
output[1] <= mux4:inst3.result[1]
output[2] <= mux4:inst3.result[2]
output[3] <= mux4:inst3.result[3]
output[4] <= mux4:inst3.result[4]
output[5] <= mux4:inst3.result[5]
output[6] <= mux4:inst3.result[6]
output[7] <= mux4:inst3.result[7]
output[8] <= mux4:inst3.result[8]
output[9] <= mux4:inst3.result[9]
output[10] <= mux4:inst3.result[10]
output[11] <= mux4:inst3.result[11]
wren => ram:inst7.wren
rden => ram:inst7.rden
wrclock => ram:inst7.wrclock
clk => ram:inst7.rdclock
clk => square:inst2.clock
clk => cos_rom:inst1.clock
clk => sin_rom:inst.clock
data[0] => ram:inst7.data[0]
data[1] => ram:inst7.data[1]
data[2] => ram:inst7.data[2]
data[3] => ram:inst7.data[3]
data[4] => ram:inst7.data[4]
data[5] => ram:inst7.data[5]
data[6] => ram:inst7.data[6]
data[7] => ram:inst7.data[7]
data[8] => ram:inst7.data[8]
data[9] => ram:inst7.data[9]
data[10] => ram:inst7.data[10]
data[11] => ram:inst7.data[11]
data[12] => ram:inst7.data[12]
data[13] => ram:inst7.data[13]
data[14] => ram:inst7.data[14]
data[15] => ram:inst7.data[15]
phasein[0] => square:inst2.address[0]
phasein[0] => cos_rom:inst1.address[0]
phasein[0] => sin_rom:inst.address[0]
phasein[1] => square:inst2.address[1]
phasein[1] => cos_rom:inst1.address[1]
phasein[1] => sin_rom:inst.address[1]
phasein[2] => square:inst2.address[2]
phasein[2] => cos_rom:inst1.address[2]
phasein[2] => sin_rom:inst.address[2]
phasein[3] => ram:inst7.rdaddress[0]
phasein[3] => square:inst2.address[3]
phasein[3] => cos_rom:inst1.address[3]
phasein[3] => sin_rom:inst.address[3]
phasein[4] => ram:inst7.rdaddress[1]
phasein[4] => square:inst2.address[4]
phasein[4] => cos_rom:inst1.address[4]
phasein[4] => sin_rom:inst.address[4]
phasein[5] => ram:inst7.rdaddress[2]
phasein[5] => square:inst2.address[5]
phasein[5] => cos_rom:inst1.address[5]
phasein[5] => sin_rom:inst.address[5]
phasein[6] => ram:inst7.rdaddress[3]
phasein[6] => square:inst2.address[6]
phasein[6] => cos_rom:inst1.address[6]
phasein[6] => sin_rom:inst.address[6]
phasein[7] => ram:inst7.rdaddress[4]
phasein[7] => square:inst2.address[7]
phasein[7] => cos_rom:inst1.address[7]
phasein[7] => sin_rom:inst.address[7]
phasein[8] => ram:inst7.rdaddress[5]
phasein[8] => square:inst2.address[8]
phasein[8] => cos_rom:inst1.address[8]
phasein[8] => sin_rom:inst.address[8]
phasein[9] => ram:inst7.rdaddress[6]
phasein[9] => square:inst2.address[9]
phasein[9] => cos_rom:inst1.address[9]
phasein[9] => sin_rom:inst.address[9]
phasein[10] => ram:inst7.rdaddress[7]
phasein[10] => square:inst2.address[10]
phasein[10] => cos_rom:inst1.address[10]
phasein[10] => sin_rom:inst.address[10]
phasein[11] => ram:inst7.rdaddress[8]
phasein[11] => square:inst2.address[11]
phasein[11] => cos_rom:inst1.address[11]
phasein[11] => sin_rom:inst.address[11]
wraddress[0] => ram:inst7.wraddress[0]
wraddress[1] => ram:inst7.wraddress[1]
wraddress[2] => ram:inst7.wraddress[2]
wraddress[3] => ram:inst7.wraddress[3]
wraddress[4] => ram:inst7.wraddress[4]
wraddress[5] => ram:inst7.wraddress[5]
wraddress[6] => ram:inst7.wraddress[6]
wraddress[7] => ram:inst7.wraddress[7]
wraddress[8] => ram:inst7.wraddress[8]
select[0] => mux4:inst3.sel[0]
select[1] => mux4:inst3.sel[1]


|dds|mux4:inst3
data0x[0] => lpm_mux:lpm_mux_component.data[0][0]
data0x[1] => lpm_mux:lpm_mux_component.data[0][1]
data0x[2] => lpm_mux:lpm_mux_component.data[0][2]
data0x[3] => lpm_mux:lpm_mux_component.data[0][3]
data0x[4] => lpm_mux:lpm_mux_component.data[0][4]
data0x[5] => lpm_mux:lpm_mux_component.data[0][5]
data0x[6] => lpm_mux:lpm_mux_component.data[0][6]
data0x[7] => lpm_mux:lpm_mux_component.data[0][7]
data0x[8] => lpm_mux:lpm_mux_component.data[0][8]
data0x[9] => lpm_mux:lpm_mux_component.data[0][9]
data0x[10] => lpm_mux:lpm_mux_component.data[0][10]
data0x[11] => lpm_mux:lpm_mux_component.data[0][11]
data1x[0] => lpm_mux:lpm_mux_component.data[1][0]
data1x[1] => lpm_mux:lpm_mux_component.data[1][1]
data1x[2] => lpm_mux:lpm_mux_component.data[1][2]
data1x[3] => lpm_mux:lpm_mux_component.data[1][3]
data1x[4] => lpm_mux:lpm_mux_component.data[1][4]
data1x[5] => lpm_mux:lpm_mux_component.data[1][5]
data1x[6] => lpm_mux:lpm_mux_component.data[1][6]
data1x[7] => lpm_mux:lpm_mux_component.data[1][7]
data1x[8] => lpm_mux:lpm_mux_component.data[1][8]
data1x[9] => lpm_mux:lpm_mux_component.data[1][9]
data1x[10] => lpm_mux:lpm_mux_component.data[1][10]
data1x[11] => lpm_mux:lpm_mux_component.data[1][11]
data2x[0] => lpm_mux:lpm_mux_component.data[2][0]
data2x[1] => lpm_mux:lpm_mux_component.data[2][1]
data2x[2] => lpm_mux:lpm_mux_component.data[2][2]
data2x[3] => lpm_mux:lpm_mux_component.data[2][3]
data2x[4] => lpm_mux:lpm_mux_component.data[2][4]
data2x[5] => lpm_mux:lpm_mux_component.data[2][5]
data2x[6] => lpm_mux:lpm_mux_component.data[2][6]
data2x[7] => lpm_mux:lpm_mux_component.data[2][7]
data2x[8] => lpm_mux:lpm_mux_component.data[2][8]
data2x[9] => lpm_mux:lpm_mux_component.data[2][9]
data2x[10] => lpm_mux:lpm_mux_component.data[2][10]
data2x[11] => lpm_mux:lpm_mux_component.data[2][11]
data3x[0] => lpm_mux:lpm_mux_component.data[3][0]
data3x[1] => lpm_mux:lpm_mux_component.data[3][1]
data3x[2] => lpm_mux:lpm_mux_component.data[3][2]
data3x[3] => lpm_mux:lpm_mux_component.data[3][3]
data3x[4] => lpm_mux:lpm_mux_component.data[3][4]
data3x[5] => lpm_mux:lpm_mux_component.data[3][5]
data3x[6] => lpm_mux:lpm_mux_component.data[3][6]
data3x[7] => lpm_mux:lpm_mux_component.data[3][7]
data3x[8] => lpm_mux:lpm_mux_component.data[3][8]
data3x[9] => lpm_mux:lpm_mux_component.data[3][9]
data3x[10] => lpm_mux:lpm_mux_component.data[3][10]
data3x[11] => lpm_mux:lpm_mux_component.data[3][11]
sel[0] => lpm_mux:lpm_mux_component.sel[0]
sel[1] => lpm_mux:lpm_mux_component.sel[1]
result[0] <= lpm_mux:lpm_mux_component.result[0]
result[1] <= lpm_mux:lpm_mux_component.result[1]
result[2] <= lpm_mux:lpm_mux_component.result[2]
result[3] <= lpm_mux:lpm_mux_component.result[3]
result[4] <= lpm_mux:lpm_mux_component.result[4]
result[5] <= lpm_mux:lpm_mux_component.result[5]
result[6] <= lpm_mux:lpm_mux_component.result[6]
result[7] <= lpm_mux:lpm_mux_component.result[7]
result[8] <= lpm_mux:lpm_mux_component.result[8]
result[9] <= lpm_mux:lpm_mux_component.result[9]
result[10] <= lpm_mux:lpm_mux_component.result[10]
result[11] <= lpm_mux:lpm_mux_component.result[11]


|dds|mux4:inst3|lpm_mux:lpm_mux_component
data[0][0] => mux_ogc:auto_generated.data[0]
data[0][1] => mux_ogc:auto_generated.data[1]
data[0][2] => mux_ogc:auto_generated.data[2]
data[0][3] => mux_ogc:auto_generated.data[3]
data[0][4] => mux_ogc:auto_generated.data[4]
data[0][5] => mux_ogc:auto_generated.data[5]
data[0][6] => mux_ogc:auto_generated.data[6]
data[0][7] => mux_ogc:auto_generated.data[7]
data[0][8] => mux_ogc:auto_generated.data[8]
data[0][9] => mux_ogc:auto_generated.data[9]
data[0][10] => mux_ogc:auto_generated.data[10]
data[0][11] => mux_ogc:auto_generated.data[11]
data[1][0] => mux_ogc:auto_generated.data[12]
data[1][1] => mux_ogc:auto_generated.data[13]
data[1][2] => mux_ogc:auto_generated.data[14]
data[1][3] => mux_ogc:auto_generated.data[15]
data[1][4] => mux_ogc:auto_generated.data[16]
data[1][5] => mux_ogc:auto_generated.data[17]
data[1][6] => mux_ogc:auto_generated.data[18]
data[1][7] => mux_ogc:auto_generated.data[19]
data[1][8] => mux_ogc:auto_generated.data[20]
data[1][9] => mux_ogc:auto_generated.data[21]
data[1][10] => mux_ogc:auto_generated.data[22]
data[1][11] => mux_ogc:auto_generated.data[23]
data[2][0] => mux_ogc:auto_generated.data[24]
data[2][1] => mux_ogc:auto_generated.data[25]
data[2][2] => mux_ogc:auto_generated.data[26]
data[2][3] => mux_ogc:auto_generated.data[27]
data[2][4] => mux_ogc:auto_generated.data[28]
data[2][5] => mux_ogc:auto_generated.data[29]
data[2][6] => mux_ogc:auto_generated.data[30]
data[2][7] => mux_ogc:auto_generated.data[31]
data[2][8] => mux_ogc:auto_generated.data[32]
data[2][9] => mux_ogc:auto_generated.data[33]
data[2][10] => mux_ogc:auto_generated.data[34]
data[2][11] => mux_ogc:auto_generated.data[35]
data[3][0] => mux_ogc:auto_generated.data[36]
data[3][1] => mux_ogc:auto_generated.data[37]
data[3][2] => mux_ogc:auto_generated.data[38]
data[3][3] => mux_ogc:auto_generated.data[39]
data[3][4] => mux_ogc:auto_generated.data[40]
data[3][5] => mux_ogc:auto_generated.data[41]
data[3][6] => mux_ogc:auto_generated.data[42]
data[3][7] => mux_ogc:auto_generated.data[43]
data[3][8] => mux_ogc:auto_generated.data[44]
data[3][9] => mux_ogc:auto_generated.data[45]
data[3][10] => mux_ogc:auto_generated.data[46]
data[3][11] => mux_ogc:auto_generated.data[47]
sel[0] => mux_ogc:auto_generated.sel[0]
sel[1] => mux_ogc:auto_generated.sel[1]
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= mux_ogc:auto_generated.result[0]
result[1] <= mux_ogc:auto_generated.result[1]
result[2] <= mux_ogc:auto_generated.result[2]
result[3] <= mux_ogc:auto_generated.result[3]
result[4] <= mux_ogc:auto_generated.result[4]
result[5] <= mux_ogc:auto_generated.result[5]
result[6] <= mux_ogc:auto_generated.result[6]
result[7] <= mux_ogc:auto_generated.result[7]
result[8] <= mux_ogc:auto_generated.result[8]
result[9] <= mux_ogc:auto_generated.result[9]
result[10] <= mux_ogc:auto_generated.result[10]
result[11] <= mux_ogc:auto_generated.result[11]


|dds|mux4:inst3|lpm_mux:lpm_mux_component|mux_ogc:auto_generated
result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE
result[8] <= result_node[8].DB_MAX_OUTPUT_PORT_TYPE
result[9] <= result_node[9].DB_MAX_OUTPUT_PORT_TYPE
result[10] <= result_node[10].DB_MAX_OUTPUT_PORT_TYPE
result[11] <= result_node[11].DB_MAX_OUTPUT_PORT_TYPE


|dds|ram:inst7
data[0] => altsyncram:altsyncram_component.data_a[0]
data[1] => altsyncram:altsyncram_component.data_a[1]
data[2] => altsyncram:altsyncram_component.data_a[2]
data[3] => altsyncram:altsyncram_component.data_a[3]
data[4] => altsyncram:altsyncram_component.data_a[4]
data[5] => altsyncram:altsyncram_component.data_a[5]
data[6] => altsyncram:altsyncram_component.data_a[6]
data[7] => altsyncram:altsyncram_component.data_a[7]
data[8] => altsyncram:altsyncram_component.data_a[8]
data[9] => altsyncram:altsyncram_component.data_a[9]
data[10] => altsyncram:altsyncram_component.data_a[10]
data[11] => altsyncram:altsyncram_component.data_a[11]
data[12] => altsyncram:altsyncram_component.data_a[12]
data[13] => altsyncram:altsyncram_component.data_a[13]
data[14] => altsyncram:altsyncram_component.data_a[14]
data[15] => altsyncram:altsyncram_component.data_a[15]
rdaddress[0] => altsyncram:altsyncram_component.address_b[0]
rdaddress[1] => altsyncram:altsyncram_component.address_b[1]
rdaddress[2] => altsyncram:altsyncram_component.address_b[2]
rdaddress[3] => altsyncram:altsyncram_component.address_b[3]
rdaddress[4] => altsyncram:altsyncram_component.address_b[4]
rdaddress[5] => altsyncram:altsyncram_component.address_b[5]
rdaddress[6] => altsyncram:altsyncram_component.address_b[6]
rdaddress[7] => altsyncram:altsyncram_component.address_b[7]
rdaddress[8] => altsyncram:altsyncram_component.address_b[8]
rdclock => altsyncram:altsyncram_component.clock1
rden => altsyncram:altsyncram_component.rden_b
wraddress[0] => altsyncram:altsyncram_component.address_a[0]
wraddress[1] => altsyncram:altsyncram_component.address_a[1]
wraddress[2] => altsyncram:altsyncram_component.address_a[2]
wraddress[3] => altsyncram:altsyncram_component.address_a[3]
wraddress[4] => altsyncram:altsyncram_component.address_a[4]
wraddress[5] => altsyncram:altsyncram_component.address_a[5]
wraddress[6] => altsyncram:altsyncram_component.address_a[6]
wraddress[7] => altsyncram:altsyncram_component.address_a[7]
wraddress[8] => altsyncram:altsyncram_component.address_a[8]
wrclock => altsyncram:altsyncram_component.clock0
wren => altsyncram:altsyncram_component.wren_a
q[0] <= altsyncram:altsyncram_component.q_b[0]
q[1] <= altsyncram:altsyncram_component.q_b[1]
q[2] <= altsyncram:altsyncram_component.q_b[2]
q[3] <= altsyncram:altsyncram_component.q_b[3]
q[4] <= altsyncram:altsyncram_component.q_b[4]
q[5] <= altsyncram:altsyncram_component.q_b[5]
q[6] <= altsyncram:altsyncram_component.q_b[6]
q[7] <= altsyncram:altsyncram_component.q_b[7]
q[8] <= altsyncram:altsyncram_component.q_b[8]
q[9] <= altsyncram:altsyncram_component.q_b[9]
q[10] <= altsyncram:altsyncram_component.q_b[10]
q[11] <= altsyncram:altsyncram_component.q_b[11]
q[12] <= altsyncram:altsyncram_component.q_b[12]
q[13] <= altsyncram:altsyncram_component.q_b[13]
q[14] <= altsyncram:altsyncram_component.q_b[14]
q[15] <= altsyncram:altsyncram_component.q_b[15]


|dds|ram:inst7|altsyncram:altsyncram_component
wren_a => altsyncram_vpl1:auto_generated.wren_a
wren_b => ~NO_FANOUT~
rden_b => altsyncram_vpl1:auto_generated.rden_b
data_a[0] => altsyncram_vpl1:auto_generated.data_a[0]
data_a[1] => altsyncram_vpl1:auto_generated.data_a[1]
data_a[2] => altsyncram_vpl1:auto_generated.data_a[2]
data_a[3] => altsyncram_vpl1:auto_generated.data_a[3]
data_a[4] => altsyncram_vpl1:auto_generated.data_a[4]
data_a[5] => altsyncram_vpl1:auto_generated.data_a[5]
data_a[6] => altsyncram_vpl1:auto_generated.data_a[6]
data_a[7] => altsyncram_vpl1:auto_generated.data_a[7]
data_a[8] => altsyncram_vpl1:auto_generated.data_a[8]
data_a[9] => altsyncram_vpl1:auto_generated.data_a[9]
data_a[10] => altsyncram_vpl1:auto_generated.data_a[10]
data_a[11] => altsyncram_vpl1:auto_generated.data_a[11]
data_a[12] => altsyncram_vpl1:auto_generated.data_a[12]
data_a[13] => altsyncram_vpl1:auto_generated.data_a[13]