phase_test.fnsim.qmsg

verilog编写基于fpga的鉴相器模块

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 19 19:35:54 2007 " "Info: Processing started: Sun Aug 19 19:35:54 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off phase_test -c phase_test --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off phase_test -c phase_test --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../phase_test.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../phase_test.v" { { "Info" "ISGN_ENTITY_NAME" "1 phase_test " "Info: Found entity 1: phase_test" {  } { { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../phase_control.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../phase_control.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 phase_control " "Info: Found entity 1: phase_control" {  } { { "../phase_control.bdf" "" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "phase_control " "Info: Elaborating entity \"phase_control\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "phase_test phase_test:inst " "Info: Elaborating entity \"phase_test\" for hierarchy \"phase_test:inst\"" {  } { { "../phase_control.bdf" "inst" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 104 160 368 264 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 phase_test.v(75) " "Warning (10230): Verilog HDL assignment warning at phase_test.v(75): truncated value with size 32 to match size of target (16)" {  } { { "../phase_test.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test.v" 75 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "phase_counter.v 1 1 " "Warning: Using design file phase_counter.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 phase_counter " "Info: Found entity 1: phase_counter" {  } { { "phase_counter.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test/phase_counter.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "phase_counter phase_counter:inst1 " "Info: Elaborating entity \"phase_counter\" for hierarchy \"phase_counter:inst1\"" {  } { { "../phase_control.bdf" "inst1" { Schematic "F:/fpga test/校赛(1) 鉴相/phase_control.bdf" { { 120 448 592 248 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../altera/quartus60/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus60/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter phase_counter:inst1\|lpm_counter:lpm_counter_component " "Info: Elaborating entity \"lpm_counter\" for hierarchy \"phase_counter:inst1\|lpm_counter:lpm_counter_component\"" {  } { { "phase_counter.v" "lpm_counter_component" { Text "F:/fpga test/校赛(1) 鉴相/phase_test/phase_counter.v" 65 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "phase_counter:inst1\|lpm_counter:lpm_counter_component " "Info: Elaborated megafunction instantiation \"phase_counter:inst1\|lpm_counter:lpm_counter_component\"" {  } { { "phase_counter.v" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test/phase_counter.v" 65 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_2ii.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_2ii.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_2ii " "Info: Found entity 1: cntr_2ii" {  } { { "db/cntr_2ii.tdf" "" { Text "F:/fpga test/校赛(1) 鉴相/phase_test/db/cntr_2ii.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_2ii phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated " "Info: Elaborating entity \"cntr_2ii\" for hierarchy \"phase_counter:inst1\|lpm_counter:lpm_counter_component\|cntr_2ii:auto_generated\"" {  } { { "lpm_counter.tdf" "auto_generated" { Text "f:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 257 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}