phase_test.tan.summary

verilog编写基于fpga的鉴相器模块

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 8.371 ns
From           : cs_phase
To             : phase_test:inst|COUNTNUM[0]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 8.332 ns
From           : phase_test:inst|COUNTNUM[29]
To             : phase_result[29]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 0.153 ns
From           : gatein[14]
To             : phase_test:inst|gatelim[14]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : 0.303 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : N/A
From           : phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[29]
To             : phase_test:inst|COUNTNUM[29]
From Clock     : phase_pll:inst12|altpll:altpll_component|_clk0
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'phase_pll:inst12|altpll:altpll_component|_clk0'
Slack          : 4.530 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : N/A
From           : phase_test:inst|sclr
To             : phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[6]
From Clock     : clk
To Clock       : phase_pll:inst12|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Setup: 'phaseinB'
Slack          : N/A
Required Time  : None
Actual Time    : 127.80 MHz ( period = 7.825 ns )
From           : phase_test:inst|counttemp[15]
To             : phase_test:inst|counttemp[14]
From Clock     : phaseinB
To Clock       : phaseinB
Failed Paths   : 0

Type           : Clock Setup: 'phaseinA'
Slack          : N/A
Required Time  : None
Actual Time    : 127.80 MHz ( period = 7.825 ns )
From           : phase_test:inst|counttemp[15]
To             : phase_test:inst|counttemp[14]
From Clock     : phaseinA
To Clock       : phaseinA
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : 1.031 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : N/A
From           : phase_test:inst|PLLEN
To             : phase_test:inst|PLLEN
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Hold: 'phase_pll:inst12|altpll:altpll_component|_clk0'
Slack          : 1.064 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : N/A
From           : phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[31]
To             : phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[31]
From Clock     : phase_pll:inst12|altpll:altpll_component|_clk0
To Clock       : phase_pll:inst12|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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