clock_my.vhd

来自「实光电码盘的输出数据的四倍频」· VHDL 代码 · 共 74 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;


ENTITY CLOCK_MY IS 
	PORT( 	 CLK       : IN  STD_LOGIC;					 	--CPLD系统时钟	
	 	
			 SENSOR_A  : IN  STD_LOGIC;					 	--码盘A信号
			 SENSOR_B  : IN  STD_LOGIC;					 	--码盘B信号
			
			 CLR       : IN  STD_LOGIC;					 	--计数器清零信号
			 READ_OE   : IN  STD_LOGIC;						--单片机读信号，高电平有效
			 READ_ADD  : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);  --32位计数器，输出选择位
			 												--当00--1-8位，01--9-16位，
															--当10--17-24位,11--25-32位
		     DATA_OUT  : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) 	--数据输出	
		 );
END CLOCK_MY;



ARCHITECTURE CLOCK_MY_1 OF CLOCK_MY IS

 	SIGNAL  COUNTER     :  STD_LOGIC_VECTOR(31 DOWNTO 0);  	  --32位计数器
	SIGNAL  SENSOR_AB   :  STD_LOGIC_VECTOR(3 DOWNTO 0);	  --码盘状态:
															  --第四位上一次SENSOR_A
															  --第三位上一次SENSOR_B
															  --第二位现在SENSOR_A
															  --第一位现在SENSOR_B
BEGIN   


	PROCESS (CLK)--CLR,READ_OE,READ_ADD)	
	BEGIN	
		IF   CLR = '1'  THEN  
		        COUNTER   <= (OTHERS=>'0');
			    SENSOR_AB <= (OTHERS=>'0');			
		ELSE 
		     IF READ_OE = '1' THEN 
		           IF READ_ADD ="00" THEN  	
	                  DATA_OUT( 7 DOWNTO 0 ) <= COUNTER(  7 DOWNTO 0 );  
		         ELSIF READ_ADD ="01" THEN
		              DATA_OUT( 7 DOWNTO 0 ) <= COUNTER( 15 DOWNTO 8 );  
		         ELSIF READ_ADD ="10" THEN
					  DATA_OUT( 7 DOWNTO 0 ) <= COUNTER( 23 DOWNTO 16 );
				 ELSIF READ_ADD ="11" THEN  
					  DATA_OUT( 7 DOWNTO 0 ) <= COUNTER( 31 DOWNTO 24 ); 
		         END IF;
		     ELSE DATA_OUT <= (OTHERS=>'Z');
		     END IF;
		
             IF CLK'EVENT AND ( CLK = '1' ) AND ( CLK'LAST_VALUE = '0' ) THEN		   
				 SENSOR_AB(1) <= SENSOR_A;               --仿真结果显示语句并行执行
				 SENSOR_AB(0) <= SENSOR_B; 
				 SENSOR_AB(3 DOWNTO 2) <= SENSOR_AB(1 DOWNTO 0);     				         					  
			  	 CASE  SENSOR_AB IS 
	 			    WHEN  "0001"  => COUNTER <= COUNTER - 1;
					WHEN  "0111"  => COUNTER <= COUNTER - 1;
					WHEN  "1110"  => COUNTER <= COUNTER - 1;
					WHEN  "1000"  => COUNTER <= COUNTER - 1;					
					WHEN  "0010"  => COUNTER <= COUNTER + 1;
					WHEN  "1011"  => COUNTER <= COUNTER + 1;
					WHEN  "1101"  => COUNTER <= COUNTER + 1;
					WHEN  "0100"  => COUNTER <= COUNTER + 1;					
					WHEN  OTHERS  => COUNTER <= COUNTER;
              	END CASE;			  
	  	     END IF;	    --  CLK'EVENT 
	    END IF;             --  CLR = '1'
	END PROCESS; 		

END ARCHITECTURE CLOCK_MY_1;