lab1.fit.summary

来自「如何如何使用verilog Hdl以及如何使其在FPGA开发板上实现」· SUMMARY 代码 · 共 13 行

Fitter Status : Successful - Fri May 09 11:02:45 2008
Quartus II Version : 7.2 Build 203 02/05/2008 SP 2 SJ Full Version
Revision Name : Lab1
Top-level Entity Name : Lab1
Family : Cyclone
Device : EP1C6Q240C8
Timing Models : Final
Total logic elements : 2 / 5,980 ( < 1 % )
Total pins : 4 / 185 ( 2 % )
Total virtual pins : 0
Total memory bits : 0 / 92,160 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )