lab1.tan.summary

如何如何使用verilog Hdl以及如何使其在FPGA开发板上实现

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 11.894 ns
From           : in2
To             : out2
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------