lab1.flow.rpt

如何如何使用verilog Hdl以及如何使其在FPGA开发板上实现

Flow report for Lab1
Fri May 09 11:02:52 2008
Quartus II Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Non-Default Global Settings
  5. Flow Elapsed Time
  6. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------+
; Flow Summary                                                             ;
+--------------------------+-----------------------------------------------+
; Flow Status              ; Successful - Fri May 09 11:02:52 2008         ;
; Quartus II Version       ; 7.2 Build 203 02/05/2008 SP 2 SJ Full Version ;
; Revision Name            ; Lab1                                          ;
; Top-level Entity Name    ; Lab1                                          ;
; Family                   ; Cyclone                                       ;
; Device                   ; EP1C6Q240C8                                   ;
; Timing Models            ; Final                                         ;
; Met timing requirements  ; Yes                                           ;
; Total logic elements     ; 2 / 5,980 ( < 1 % )                           ;
; Total pins               ; 4 / 185 ( 2 % )                               ;
; Total virtual pins       ; 0                                             ;
; Total memory bits        ; 0 / 92,160 ( 0 % )                            ;
; DSP block 9-bit elements ; N/A until Partition Merge                     ;
; Total PLLs               ; 0 / 2 ( 0 % )                                 ;
; Total DLLs               ; N/A until Partition Merge                     ;
+--------------------------+-----------------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 05/09/2008 11:02:30 ;
; Main task         ; Compilation         ;
; Revision Name     ; Lab1                ;
+-------------------+---------------------+


+-----------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings                                                        ;
+------------------------------------+---------+---------------+-------------+------------+
; Assignment Name                    ; Value   ; Default Value ; Entity Name ; Section Id ;
+------------------------------------+---------+---------------+-------------+------------+
; PARTITION_COLOR                    ; 2147039 ; --            ; --          ; Top        ;
; PARTITION_NETLIST_TYPE             ; SOURCE  ; --            ; --          ; Top        ;
; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off     ; --            ; --          ; eda_palace ;
+------------------------------------+---------+---------------+-------------+------------+


+------------------------------------------------------------------+
; Flow Elapsed Time                                                ;
+-------------------------+--------------+-------------------------+
; Module Name             ; Elapsed Time ; Average Processors Used ;
+-------------------------+--------------+-------------------------+
; Analysis & Synthesis    ; 00:00:06     ; 1.0                     ;
; Fitter                  ; 00:00:04     ; 1.0                     ;
; Assembler               ; 00:00:03     ; 1.0                     ;
; Classic Timing Analyzer ; 00:00:01     ; 1.0                     ;
; Total                   ; 00:00:14     ; --                      ;
+-------------------------+--------------+-------------------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off Lab1_FPGA -c Lab1
quartus_fit --read_settings_files=off --write_settings_files=off Lab1_FPGA -c Lab1
quartus_asm --read_settings_files=off --write_settings_files=off Lab1_FPGA -c Lab1
quartus_tan --read_settings_files=off --write_settings_files=off Lab1_FPGA -c Lab1 --timing_analysis_only