lab1.fit.rpt

如何如何使用verilog Hdl以及如何使其在FPGA开发板上实现

Fitter report for Lab1
Fri May 09 11:02:45 2008
Quartus II Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Pin-Out File
  5. Fitter Resource Usage Summary
  6. Input Pins
  7. Output Pins
  8. I/O Bank Usage
  9. All Package Pins
 10. Output Pin Default Load For Reported TCO
 11. Fitter Resource Utilization by Entity
 12. Delay Chain Summary
 13. Pad To Core Delay Chain Fanout
 14. Non-Global High Fan-Out Signals
 15. Interconnect Usage Summary
 16. LAB Logic Elements
 17. LAB Signals Sourced
 18. LAB Signals Sourced Out
 19. LAB Distinct Inputs
 20. Fitter Device Options
 21. Advanced Data - General
 22. Advanced Data - Placement Preparation
 23. Advanced Data - Placement
 24. Advanced Data - Routing
 25. Fitter Messages
 26. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------+
; Fitter Summary                                                        ;
+-----------------------+-----------------------------------------------+
; Fitter Status         ; Successful - Fri May 09 11:02:45 2008         ;
; Quartus II Version    ; 7.2 Build 203 02/05/2008 SP 2 SJ Full Version ;
; Revision Name         ; Lab1                                          ;
; Top-level Entity Name ; Lab1                                          ;
; Family                ; Cyclone                                       ;
; Device                ; EP1C6Q240C8                                   ;
; Timing Models         ; Final                                         ;
; Total logic elements  ; 2 / 5,980 ( < 1 % )                           ;
; Total pins            ; 4 / 185 ( 2 % )                               ;
; Total virtual pins    ; 0                                             ;
; Total memory bits     ; 0 / 92,160 ( 0 % )                            ;
; Total PLLs            ; 0 / 2 ( 0 % )                                 ;
+-----------------------+-----------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                      ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                             ; Setting                        ; Default Value                  ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                             ; EP1C6Q240C8                    ;                                ;
; Fit Attempts to Skip                                               ; 0                              ; 0.0                            ;
; Use smart compilation                                              ; Off                            ; Off                            ;
; Maximum processors allowed for parallel compilation                ; 1                              ; 1                              ;
; Use TimeQuest Timing Analyzer                                      ; Off                            ; Off                            ;
; Router Timing Optimization Level                                   ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                        ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                        ; Off                            ; Off                            ;
; Equivalent RAM and MLAB Paused Read Capabilities                   ; Care                           ; Care                           ;
; Optimize Timing                                                    ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                         ; On                             ; On                             ;
; Limit to One Fitting Attempt                                       ; Off                            ; Off                            ;
; Final Placement Optimizations                                      ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                        ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                      ; 1                              ; 1                              ;
; Slow Slew Rate                                                     ; Off                            ; Off                            ;
; PCI I/O                                                            ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                          ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                 ; Off                            ; Off                            ;
; Auto Packed Registers -- Cyclone                                   ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                  ; On                             ; On                             ;
; Auto Merge PLLs                                                    ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                       ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                          ; Off                            ; Off                            ;