lab1_fpga.qws

来自「如何如何使用verilog Hdl以及如何使其在FPGA开发板上实现」· QWS 代码 · 共 33 行

[ProjectWorkspace]
ptn_Child1=Frames
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
ptn_Child2=Document-1
ptn_Child3=Document-2
ptn_Child4=Document-3
ptn_Child5=Document-4
[ProjectWorkspace.Frames.ChildFrames.Document-1]
ptn_Child1=ViewFrame-0
[ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0]
DocPathName=Lab1.v
DocumentCLSID={84678d98-dc76-11d0-a0d8-0020affa5bde}
IsChildFrameDetached=False
IsActiveChildFrame=False
ptn_Child1=StateMap
[ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0.StateMap]
AFC_IN_REPORT=False
[ProjectWorkspace.Frames.ChildFrames.Document-2]
ptn_Child1=ViewFrame-0
[ProjectWorkspace.Frames.ChildFrames.Document-2.ViewFrame-0]
DocPathName=c:/altera/72/quartus/bin/pin_planner.ppl
DocumentCLSID={428be327-2a68-4a16-a2c9-0502a8811afc}
IsChildFrameDetached=False
IsActiveChildFrame=False
ptn_Child1=StateMap
[ProjectWorkspace.Frames.ChildFrames.Document-2.ViewFrame-0.StateMap]
AFC_CMP_AP_NAME=Lab1
AFC_PROJ_DB_PATH=E:/Lab1_FPGA/db/Lab1_FPGA.quartus_db
AFC_IN_REPORT=False