lab1.map.summary

来自「如何如何使用verilog Hdl以及如何使其在FPGA开发板上实现」· SUMMARY 代码 · 共 13 行

Analysis & Synthesis Status : Successful - Fri May 09 11:02:34 2008
Quartus II Version : 7.2 Build 203 02/05/2008 SP 2 SJ Full Version
Revision Name : Lab1
Top-level Entity Name : Lab1
Family : Cyclone
Total logic elements : 2
Total pins : 4
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : N/A until Partition Merge
Total PLLs : 0
Total DLLs : N/A until Partition Merge