maincontrol.tan.rpt

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

+-------+----------------------------------+-------------+--------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)             ; From        ; To                 ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+----------------------------------+-------------+--------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[0] ; Alarmclock_EN~reg0 ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[1] ; Alarmclock_EN~reg0 ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[2] ; Alarmclock_EN~reg0 ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[0] ; TimeSet_EN~reg0    ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[1] ; TimeSet_EN~reg0    ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[2] ; TimeSet_EN~reg0    ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[0] ; DateSet_EN~reg0    ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[1] ; DateSet_EN~reg0    ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[2] ; DateSet_EN~reg0    ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[0] ; Date_EN~reg0       ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[1] ; Date_EN~reg0       ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[2] ; Date_EN~reg0       ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[0] ; Stopwatch_EN~reg0  ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[1] ; Stopwatch_EN~reg0  ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[2] ; Stopwatch_EN~reg0  ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[0] ; Timepiece_EN~reg0  ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[1] ; Timepiece_EN~reg0  ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[2] ; Timepiece_EN~reg0  ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[0] ; Function[2]        ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[1] ; Function[2]        ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[2] ; Function[2]        ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[0] ; Function[1]        ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[1] ; Function[1]        ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[2] ; Function[1]        ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[0] ; Function[0]        ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[1] ; Function[0]        ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[2] ; Function[0]        ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
+-------+----------------------------------+-------------+--------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------------------------------+
; tco                                                                                 ;
+-------+--------------+------------+--------------------+---------------+------------+
; Slack ; Required tco ; Actual tco ; From               ; To            ; From Clock ;
+-------+--------------+------------+--------------------+---------------+------------+
; N/A   ; None         ; 2.800 ns   ; Alarmclock_EN~reg0 ; Alarmclock_EN ; SW3        ;
; N/A   ; None         ; 2.800 ns   ; TimeSet_EN~reg0    ; TimeSet_EN    ; SW3        ;
; N/A   ; None         ; 2.800 ns   ; DateSet_EN~reg0    ; DateSet_EN    ; SW3        ;
; N/A   ; None         ; 2.800 ns   ; Date_EN~reg0       ; Date_EN       ; SW3        ;
; N/A   ; None         ; 2.800 ns   ; Stopwatch_EN~reg0  ; Stopwatch_EN  ; SW3        ;
; N/A   ; None         ; 2.800 ns   ; Timepiece_EN~reg0  ; Timepiece_EN  ; SW3        ;
+-------+--------------+------------+--------------------+---------------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Sat Jul 15 14:59:31 2006
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off maincontrol -c maincontrol
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "SW3" is an undefined clock
Info: Clock "SW3" has Internal fmax of 175.44 MHz between source register "Function[0]" and destination register "Alarmclock_EN~reg0" (period= 5.7 ns)
    Info: + Longest register to register delay is 3.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC15; Fanout = 12; REG Node = 'Function[0]'
        Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC7; Fanout = 1; REG Node = 'Alarmclock_EN~reg0'
        Info: Total cell delay = 2.600 ns ( 72.22 % )
        Info: Total interconnect delay = 1.000 ns ( 27.78 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "SW3" to destination register is 1.300 ns
            Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'SW3'
            Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC7; Fanout = 1; REG Node = 'Alarmclock_EN~reg0'
            Info: Total cell delay = 1.300 ns ( 100.00 % )
        Info: - Longest clock path from clock "SW3" to source register is 1.300 ns
            Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'SW3'
            Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC15; Fanout = 12; REG Node = 'Function[0]'
            Info: Total cell delay = 1.300 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.300 ns
    Info: + Micro setup delay of destination is 0.800 ns
Info: tco from clock "SW3" to destination pin "Alarmclock_EN" through register "Alarmclock_EN~reg0" is 2.800 ns
    Info: + Longest clock path from clock "SW3" to source register is 1.300 ns
        Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'SW3'
        Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC7; Fanout = 1; REG Node = 'Alarmclock_EN~reg0'
        Info: Total cell delay = 1.300 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.300 ns
    Info: + Longest register to pin delay is 0.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7; Fanout = 1; REG Node = 'Alarmclock_EN~reg0'
        Info: 2: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'Alarmclock_EN'
        Info: Total cell delay = 0.200 ns ( 100.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sat Jul 15 14:59:31 2006
    Info: Elapsed time: 00:00:01