maincontrol.tan.qmsg

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "SW3 " "Info: Assuming node \"SW3\" is an undefined clock" {  } { { "maincontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/maincontrol.v" 11 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "SW3" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SW3 register Function\[0\] register Alarmclock_EN~reg0 175.44 MHz 5.7 ns Internal " "Info: Clock \"SW3\" has Internal fmax of 175.44 MHz between source register \"Function\[0\]\" and destination register \"Alarmclock_EN~reg0\" (period= 5.7 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.600 ns + Longest register register " "Info: + Longest register to register delay is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Function\[0\] 1 REG LC15 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC15; Fanout = 12; REG Node = 'Function\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" Compiler "maincontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/" "" "" { Function[0] } "NODE_NAME" } "" } } { "maincontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/maincontrol.v" 86 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 3.600 ns Alarmclock_EN~reg0 2 REG LC7 1 " "Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC7; Fanout = 1; REG Node = 'Alarmclock_EN~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" Compiler "maincontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/" "" "3.600 ns" { Function[0] Alarmclock_EN~reg0 } "NODE_NAME" } "" } } { "maincontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/maincontrol.v" 86 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 72.22 % " "Info: Total cell delay = 2.600 ns ( 72.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 27.78 % " "Info: Total interconnect delay = 1.000 ns ( 27.78 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" Compiler "maincontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/" "" "3.600 ns" { Function[0] Alarmclock_EN~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { Function[0] Alarmclock_EN~reg0 } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW3 destination 1.300 ns + Shortest register " "Info: + Shortest clock path from clock \"SW3\" to destination register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns SW3 1 CLK PIN_43 9 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'SW3'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" Compiler "maincontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/" "" "" { SW3 } "NODE_NAME" } "" } } { "maincontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/maincontrol.v" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns Alarmclock_EN~reg0 2 REG LC7 1 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC7; Fanout = 1; REG Node = 'Alarmclock_EN~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" Compiler "maincontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/" "" "0.100 ns" { SW3 Alarmclock_EN~reg0 } "NODE_NAME" } "" } } { "maincontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/maincontrol.v" 86 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" Compiler "maincontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/" "" "1.300 ns" { SW3 Alarmclock_EN~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { SW3 SW3~out Alarmclock_EN~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW3 source 1.300 ns - Longest register " "Info: - Longest clock path from clock \"SW3\" to source register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns SW3 1 CLK PIN_43 9 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'SW3'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" Compiler "maincontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/" "" "" { SW3 } "NODE_NAME" } "" } } { "maincontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/maincontrol.v" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns Function\[0\] 2 REG LC15 12 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC15; Fanout = 12; REG Node = 'Function\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" Compiler "maincontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/" "" "0.100 ns" { SW3 Function[0] } "NODE_NAME" } "" } } { "maincontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/maincontrol.v" 86 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" Compiler "maincontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/" "" "1.300 ns" { SW3 Function[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { SW3 SW3~out Function[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" Compiler "maincontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/" "" "1.300 ns" { SW3 Alarmclock_EN~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { SW3 SW3~out Alarmclock_EN~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" Compiler "maincontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/" "" "1.300 ns" { SW3 Function[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { SW3 SW3~out Function[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "maincontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/maincontrol.v" 86 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "maincontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/maincontrol.v" 86 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" Compiler "maincontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/" "" "3.600 ns" { Function[0] Alarmclock_EN~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { Function[0] Alarmclock_EN~reg0 } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" Compiler "maincontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/" "" "1.300 ns" { SW3 Alarmclock_EN~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { SW3 SW3~out Alarmclock_EN~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" Compiler "maincontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/" "" "1.300 ns" { SW3 Function[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { SW3 SW3~out Function[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "SW3 Alarmclock_EN Alarmclock_EN~reg0 2.800 ns register " "Info: tco from clock \"SW3\" to destination pin \"Alarmclock_EN\" through register \"Alarmclock_EN~reg0\" is 2.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW3 source 1.300 ns + Longest register " "Info: + Longest clock path from clock \"SW3\" to source register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns SW3 1 CLK PIN_43 9 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'SW3'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" Compiler "maincontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/" "" "" { SW3 } "NODE_NAME" } "" } } { "maincontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/maincontrol.v" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns Alarmclock_EN~reg0 2 REG LC7 1 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC7; Fanout = 1; REG Node = 'Alarmclock_EN~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" Compiler "maincontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/" "" "0.100 ns" { SW3 Alarmclock_EN~reg0 } "NODE_NAME" } "" } } { "maincontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/maincontrol.v" 86 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" Compiler "maincontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/" "" "1.300 ns" { SW3 Alarmclock_EN~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { SW3 SW3~out Alarmclock_EN~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "maincontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/maincontrol.v" 86 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.200 ns + Longest register pin " "Info: + Longest register to pin delay is 0.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Alarmclock_EN~reg0 1 REG LC7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7; Fanout = 1; REG Node = 'Alarmclock_EN~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" Compiler "maincontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/" "" "" { Alarmclock_EN~reg0 } "NODE_NAME" } "" } } { "maincontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/maincontrol.v" 86 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns Alarmclock_EN 2 PIN PIN_11 0 " "Info: 2: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'Alarmclock_EN'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" Compiler "maincontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/" "" "0.200 ns" { Alarmclock_EN~reg0 Alarmclock_EN } "NODE_NAME" } "" } } { "maincontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/maincontrol.v" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.200 ns 100.00 % " "Info: Total cell delay = 0.200 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" Compiler "maincontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/" "" "0.200 ns" { Alarmclock_EN~reg0 Alarmclock_EN } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "0.200 ns" { Alarmclock_EN~reg0 Alarmclock_EN } { 0.000ns 0.000ns } { 0.000ns 0.200ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" Compiler "maincontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/" "" "1.300 ns" { SW3 Alarmclock_EN~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { SW3 SW3~out Alarmclock_EN~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol_cmp.qrpt" Compiler "maincontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/db/maincontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/maincontrol/" "" "0.200 ns" { Alarmclock_EN~reg0 Alarmclock_EN } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "0.200 ns" { Alarmclock_EN~reg0 Alarmclock_EN } { 0.000ns 0.000ns } { 0.000ns 0.200ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jul 15 14:59:31 2006 " "Info: Processing ended: Sat Jul 15 14:59:31 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}