maincontrol.tan.summary

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 2.800 ns
From           : Timepiece_EN~reg0
To             : Timepiece_EN
From Clock     : SW3
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'SW3'
Slack          : N/A
Required Time  : None
Actual Time    : 175.44 MHz ( period = 5.700 ns )
From           : Function[2]
To             : Function[0]
From Clock     : SW3
To Clock       : SW3
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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