maincontrol.map.eqn

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

--Function[0] is Function[0]
Function[0]_p1_out = Function[1] & Function[2] & !Function[0];
Function[0]_or_out = Function[0]_p1_out;
Function[0]_reg_input = !Function[0]_or_out;
Function[0] = TFFE(Function[0]_reg_input, GLOBAL(SW3), , , );


--Function[1] is Function[1]
Function[1]_p1_out = !Function[2] & Function[1] & !Function[0];
Function[1]_p2_out = !Function[2] & !Function[1] & Function[0];
Function[1]_or_out = Function[1]_p1_out # Function[1]_p2_out;
Function[1]_reg_input = Function[1]_or_out;
Function[1] = DFFE(Function[1]_reg_input, GLOBAL(SW3), , , );


--Function[2] is Function[2]
Function[2]_p1_out = !Function[1] & !Function[2];
Function[2]_p2_out = !Function[2] & !Function[0];
Function[2]_p3_out = !Function[1] & !Function[0];
Function[2]_or_out = Function[2]_p1_out # Function[2]_p2_out # Function[2]_p3_out;
Function[2]_reg_input = !Function[2]_or_out;
Function[2] = TFFE(Function[2]_reg_input, GLOBAL(SW3), , , );


--A1L71Q is Timepiece_EN~reg0
A1L71Q_p1_out = !Function[2] & !Function[1] & !Function[0];
A1L71Q_or_out = A1L71Q_p1_out;
A1L71Q_reg_input = A1L71Q_or_out;
A1L71Q = DFFE(A1L71Q_reg_input, GLOBAL(SW3), , , );


--A1L31Q is Stopwatch_EN~reg0
A1L31Q_p1_out = !Function[2] & Function[1] & !Function[0];
A1L31Q_or_out = A1L31Q_p1_out;
A1L31Q_reg_input = A1L31Q_or_out;
A1L31Q = DFFE(A1L31Q_reg_input, GLOBAL(SW3), , , );


--A1L6Q is Date_EN~reg0
A1L6Q_p1_out = Function[2] & !Function[1] & !Function[0];
A1L6Q_or_out = A1L6Q_p1_out;
A1L6Q_reg_input = A1L6Q_or_out;
A1L6Q = DFFE(A1L6Q_reg_input, GLOBAL(SW3), , , );


--A1L4Q is DateSet_EN~reg0
A1L4Q_p1_out = Function[2] & !Function[1] & Function[0];
A1L4Q_or_out = A1L4Q_p1_out;
A1L4Q_reg_input = A1L4Q_or_out;
A1L4Q = DFFE(A1L4Q_reg_input, GLOBAL(SW3), , , );


--A1L51Q is TimeSet_EN~reg0
A1L51Q_p1_out = !Function[1] & !Function[2] & Function[0];
A1L51Q_or_out = A1L51Q_p1_out;
A1L51Q_reg_input = A1L51Q_or_out;
A1L51Q = DFFE(A1L51Q_reg_input, GLOBAL(SW3), , , );


--A1L2Q is Alarmclock_EN~reg0
A1L2Q_p1_out = Function[1] & !Function[2] & Function[0];
A1L2Q_or_out = A1L2Q_p1_out;
A1L2Q_reg_input = A1L2Q_or_out;
A1L2Q = DFFE(A1L2Q_reg_input, GLOBAL(SW3), , , );


--SW3 is SW3
--operation mode is input

SW3 = INPUT();


--Timepiece_EN is Timepiece_EN
--operation mode is output

Timepiece_EN = OUTPUT(A1L71Q);


--Stopwatch_EN is Stopwatch_EN
--operation mode is output

Stopwatch_EN = OUTPUT(A1L31Q);


--Date_EN is Date_EN
--operation mode is output

Date_EN = OUTPUT(A1L6Q);


--DateSet_EN is DateSet_EN
--operation mode is output

DateSet_EN = OUTPUT(A1L4Q);


--TimeSet_EN is TimeSet_EN
--operation mode is output

TimeSet_EN = OUTPUT(A1L51Q);


--Alarmclock_EN is Alarmclock_EN
--operation mode is output

Alarmclock_EN = OUTPUT(A1L2Q);