maincontrol.v

来自「基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码」· Verilog 代码 · 共 87 行

module maincontrol(
					SW3,
					Timepiece_EN,
					TimeSet_EN,
					Stopwatch_EN,
					Alarmclock_EN,
					Date_EN,
					DateSet_EN);

output Timepiece_EN,TimeSet_EN,Stopwatch_EN,Alarmclock_EN,Date_EN,DateSet_EN;
input  SW3;

reg Timepiece_EN,TimeSet_EN,Stopwatch_EN,Alarmclock_EN,Date_EN,DateSet_EN;
reg [2:0] Function; //存放功能号

always @(posedge SW3)
begin
  if(Function < 3'b101)
	Function <= Function + 3'b1;
  else
    Function <= 3'b0;
  case(Function)
    //时钟
    3'b000:   begin
			    Timepiece_EN  <= 1'b1;
			    TimeSet_EN    <= 1'b0;
			    Stopwatch_EN  <= 1'b0;
			    Alarmclock_EN <= 1'b0;
			    Date_EN       <= 1'b0;
			    DateSet_EN    <= 1'b0;
			  end
    //时钟设置
    3'b001:   begin
			    Timepiece_EN  <= 1'b0;
			    TimeSet_EN    <= 1'b1;
			    Stopwatch_EN  <= 1'b0;
			    Alarmclock_EN <= 1'b0;
			    Date_EN       <= 1'b0;
			    DateSet_EN    <= 1'b0;
			  end
    //秒表
    3'b010:   begin
			    Timepiece_EN  <= 1'b0;
			    TimeSet_EN    <= 1'b0;
			    Stopwatch_EN  <= 1'b1;
			    Alarmclock_EN <= 1'b0;
			    Date_EN       <= 1'b0;
			    DateSet_EN    <= 1'b0;
			  end
	//闹钟设置
    3'b011:   begin
			    Timepiece_EN  <= 1'b0;
			    TimeSet_EN    <= 1'b0;
			    Stopwatch_EN  <= 1'b0;
			    Alarmclock_EN <= 1'b1;
			    Date_EN       <= 1'b0;
			    DateSet_EN    <= 1'b0;
			  end
    //日期显示
    3'b100:   begin
			    Timepiece_EN  <= 1'b0;
			    TimeSet_EN    <= 1'b0;
			    Stopwatch_EN  <= 1'b0;
			    Alarmclock_EN <= 1'b0;
			    Date_EN       <= 1'b1;
			    DateSet_EN    <= 1'b0;
			  end
	//日期设置
	3'b101:   begin
			    Timepiece_EN  <= 1'b0;
			    TimeSet_EN    <= 1'b0;
			    Stopwatch_EN  <= 1'b0;
			    Alarmclock_EN <= 1'b0;
			    Date_EN       <= 1'b0;
			    DateSet_EN    <= 1'b1;
			  end
    default:  begin
                Timepiece_EN  <= 1'b0;
			    TimeSet_EN    <= 1'b0;
			    Stopwatch_EN  <= 1'b0;
			    Alarmclock_EN <= 1'b0;
			    Date_EN       <= 1'b0;
			    DateSet_EN    <= 1'b0;
              end
  endcase
end
endmodule