maincontrol.map.summary

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

Flow Status : Successful - Sat Jul 15 14:59:18 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : maincontrol
Top-level Entity Name : maincontrol
Family : MAX7000S
Met timing requirements : N/A
Total macrocells : 9
Total pins : 7