maincontrol.fit.summary

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

Flow Status : Successful - Sat Jul 15 14:59:24 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : maincontrol
Top-level Entity Name : maincontrol
Family : MAX7000S
Met timing requirements : N/A
Total macrocells : 9 / 32 ( 28 % )
Total pins : 11 / 36 ( 30 % )
Device : EPM7032SLC44-5
Timing Models : Final