maincontrol.fit.eqn

来自「基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码」· EQN 代码 · 共 113 行

--Function[0] is Function[0] at LC15
Function[0]_p1_out = Function[1] & Function[2] & !Function[0];
Function[0]_or_out = Function[0]_p1_out;
Function[0]_reg_input = !Function[0]_or_out;
Function[0] = TFFE(Function[0]_reg_input, GLOBAL(SW3), , , );


--Function[1] is Function[1] at LC8
Function[1]_p1_out = !Function[2] & Function[1] & !Function[0];
Function[1]_p2_out = !Function[2] & !Function[1] & Function[0];
Function[1]_or_out = Function[1]_p1_out # Function[1]_p2_out;
Function[1]_reg_input = Function[1]_or_out;
Function[1] = DFFE(Function[1]_reg_input, GLOBAL(SW3), , , );


--Function[2] is Function[2] at LC4
Function[2]_p1_out = !Function[1] & !Function[2];
Function[2]_p2_out = !Function[2] & !Function[0];
Function[2]_p3_out = !Function[1] & !Function[0];
Function[2]_or_out = Function[2]_p1_out # Function[2]_p2_out # Function[2]_p3_out;
Function[2]_reg_input = !Function[2]_or_out;
Function[2] = TFFE(Function[2]_reg_input, GLOBAL(SW3), , , );


--A1L12Q is Timepiece_EN~reg0 at LC1
A1L12Q_p1_out = !Function[2] & !Function[1] & !Function[0];
A1L12Q_or_out = A1L12Q_p1_out;
A1L12Q_reg_input = A1L12Q_or_out;
A1L12Q = DFFE(A1L12Q_reg_input, GLOBAL(SW3), , , );


--A1L31Q is Stopwatch_EN~reg0 at LC2
A1L31Q_p1_out = !Function[2] & Function[1] & !Function[0];
A1L31Q_or_out = A1L31Q_p1_out;
A1L31Q_reg_input = A1L31Q_or_out;
A1L31Q = DFFE(A1L31Q_reg_input, GLOBAL(SW3), , , );


--A1L6Q is Date_EN~reg0 at LC3
A1L6Q_p1_out = Function[2] & !Function[1] & !Function[0];
A1L6Q_or_out = A1L6Q_p1_out;
A1L6Q_reg_input = A1L6Q_or_out;
A1L6Q = DFFE(A1L6Q_reg_input, GLOBAL(SW3), , , );


--A1L4Q is DateSet_EN~reg0 at LC5
A1L4Q_p1_out = Function[2] & !Function[1] & Function[0];
A1L4Q_or_out = A1L4Q_p1_out;
A1L4Q_reg_input = A1L4Q_or_out;
A1L4Q = DFFE(A1L4Q_reg_input, GLOBAL(SW3), , , );


--A1L91Q is TimeSet_EN~reg0 at LC6
A1L91Q_p1_out = !Function[1] & !Function[2] & Function[0];
A1L91Q_or_out = A1L91Q_p1_out;
A1L91Q_reg_input = A1L91Q_or_out;
A1L91Q = DFFE(A1L91Q_reg_input, GLOBAL(SW3), , , );


--A1L2Q is Alarmclock_EN~reg0 at LC7
A1L2Q_p1_out = Function[1] & !Function[2] & Function[0];
A1L2Q_or_out = A1L2Q_p1_out;
A1L2Q_reg_input = A1L2Q_or_out;
A1L2Q = DFFE(A1L2Q_reg_input, GLOBAL(SW3), , , );


--SW3 is SW3 at PIN_43
--operation mode is input

SW3 = INPUT();


--Timepiece_EN is Timepiece_EN at PIN_4
--operation mode is output

Timepiece_EN = OUTPUT(A1L12Q);


--Stopwatch_EN is Stopwatch_EN at PIN_5
--operation mode is output

Stopwatch_EN = OUTPUT(A1L31Q);


--Date_EN is Date_EN at PIN_6
--operation mode is output

Date_EN = OUTPUT(A1L6Q);


--DateSet_EN is DateSet_EN at PIN_8
--operation mode is output

DateSet_EN = OUTPUT(A1L4Q);


--TimeSet_EN is TimeSet_EN at PIN_9
--operation mode is output

TimeSet_EN = OUTPUT(A1L91Q);


--Alarmclock_EN is Alarmclock_EN at PIN_11
--operation mode is output

Alarmclock_EN = OUTPUT(A1L2Q);