time_disp_select.fit.eqn

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

--auto_disp_drive[1] is auto_disp_drive[1] at LC16
auto_disp_drive[1]_p1_out = !auto_disp_drive[2] & auto_disp_drive[0] & !auto_disp_drive[1];
auto_disp_drive[1]_p2_out = !auto_disp_drive[2] & !auto_disp_drive[0] & auto_disp_drive[1];
auto_disp_drive[1]_or_out = auto_disp_drive[1]_p1_out # auto_disp_drive[1]_p2_out;
auto_disp_drive[1]_reg_input = auto_disp_drive[1]_or_out;
auto_disp_drive[1] = DFFE(auto_disp_drive[1]_reg_input, GLOBAL(clk_1khz), , , );


--A1L41 is clk~13 at LC25
A1L41_p1_out = Time_EN & clk_1khz;
A1L41_p2_out = !Time_EN & clk_200hz;
A1L41_or_out = A1L41_p1_out # A1L41_p2_out;
A1L41 = A1L41_or_out;


--A1L12 is disp_drive~43 at LC15
A1L12_p1_out = Time_EN & auto_disp_drive[1];
A1L12_p2_out = !Time_EN & timeset_disp_drive[1];
A1L12_or_out = A1L12_p1_out # A1L12_p2_out;
A1L12 = A1L12_or_out;


--auto_disp_drive[2] is auto_disp_drive[2] at LC14
auto_disp_drive[2]_p1_out = !auto_disp_drive[0] & !auto_disp_drive[2];
auto_disp_drive[2]_p2_out = !auto_disp_drive[2] & !auto_disp_drive[1];
auto_disp_drive[2]_p3_out = !auto_disp_drive[0] & !auto_disp_drive[1];
auto_disp_drive[2]_or_out = auto_disp_drive[2]_p1_out # auto_disp_drive[2]_p2_out # auto_disp_drive[2]_p3_out;
auto_disp_drive[2]_reg_input = !auto_disp_drive[2]_or_out;
auto_disp_drive[2] = TFFE(auto_disp_drive[2]_reg_input, GLOBAL(clk_1khz), , , );


--A1L51 is clk~24 at LC13
A1L51_p1_out = A1L41 & A1L7;
A1L51_p2_out = A1L51 & !Time_EN & !TimeSet_EN;
A1L51_p3_out = A1L41 & A1L51;
A1L51_or_out = A1L51_p1_out # A1L51_p2_out # A1L51_p3_out;
A1L51 = A1L51_or_out;


--A1L71 is disp_drive[1]~56 at LC12
A1L71_p1_out = A1L12 & A1L7;
A1L71_p2_out = A1L71 & !Time_EN & !TimeSet_EN;
A1L71_p3_out = A1L12 & A1L71;
A1L71_or_out = A1L71_p1_out # A1L71_p2_out # A1L71_p3_out;
A1L71 = A1L71_or_out;


--auto_disp_drive[0] is auto_disp_drive[0] at LC11
auto_disp_drive[0]_p1_out = auto_disp_drive[2] & auto_disp_drive[1] & !auto_disp_drive[0];
auto_disp_drive[0]_or_out = auto_disp_drive[0]_p1_out;
auto_disp_drive[0]_reg_input = !auto_disp_drive[0]_or_out;
auto_disp_drive[0] = TFFE(auto_disp_drive[0]_reg_input, GLOBAL(clk_1khz), , , );


--A1L02 is disp_drive~41 at LC10
A1L02_p1_out = Time_EN & auto_disp_drive[2];
A1L02_p2_out = !Time_EN & timeset_disp_drive[2];
A1L02_or_out = A1L02_p1_out # A1L02_p2_out;
A1L02 = A1L02_or_out;


--A1L91 is disp_drive~39 at LC9
A1L91_p1_out = auto_disp_drive[0] & Time_EN;
A1L91_p2_out = !Time_EN & timeset_disp_drive[0];
A1L91_or_out = A1L91_p1_out # A1L91_p2_out;
A1L91 = A1L91_or_out;


--A1L81 is disp_drive[2]~66 at LC8
A1L81_p1_out = A1L02 & A1L7;
A1L81_p2_out = A1L81 & !Time_EN & !TimeSet_EN;
A1L81_p3_out = A1L02 & A1L81;
A1L81_or_out = A1L81_p1_out # A1L81_p2_out # A1L81_p3_out;
A1L81 = A1L81_or_out;


--A1L61 is disp_drive[0]~70 at LC4
A1L61_p1_out = A1L91 & A1L7;
A1L61_p2_out = A1L61 & !Time_EN & !TimeSet_EN;
A1L61_p3_out = A1L91 & A1L61;
A1L61_or_out = A1L61_p1_out # A1L61_p2_out # A1L61_p3_out;
A1L61 = A1L61_or_out;


--A1L43Q is time_disp_select[5]~reg0 at LC1
A1L43Q_p1_out = !A1L61 & !A1L81 & !A1L71;
A1L43Q_or_out = A1L43Q_p1_out;
A1L43Q_reg_input = A1L43Q_or_out;
A1L43Q = DFFE(A1L43Q_reg_input, A1L51, , , );


--A1L23Q is time_disp_select[4]~reg0 at LC2
A1L23Q_p1_out = A1L61 & !A1L81 & !A1L71;
A1L23Q_or_out = A1L23Q_p1_out;
A1L23Q_reg_input = A1L23Q_or_out;
A1L23Q = DFFE(A1L23Q_reg_input, A1L51, , , );


--A1L03Q is time_disp_select[3]~reg0 at LC3
A1L03Q_p1_out = !A1L61 & !A1L81 & A1L71;
A1L03Q_or_out = A1L03Q_p1_out;
A1L03Q_reg_input = A1L03Q_or_out;
A1L03Q = DFFE(A1L03Q_reg_input, A1L51, , , );


--A1L82Q is time_disp_select[2]~reg0 at LC5
A1L82Q_p1_out = A1L61 & !A1L81 & A1L71;
A1L82Q_or_out = A1L82Q_p1_out;
A1L82Q_reg_input = A1L82Q_or_out;
A1L82Q = DFFE(A1L82Q_reg_input, A1L51, , , );


--A1L62Q is time_disp_select[1]~reg0 at LC6
A1L62Q_p1_out = !A1L61 & A1L81 & !A1L71;
A1L62Q_or_out = A1L62Q_p1_out;
A1L62Q_reg_input = A1L62Q_or_out;
A1L62Q = DFFE(A1L62Q_reg_input, A1L51, , , );


--A1L42Q is time_disp_select[0]~reg0 at LC7
A1L42Q_p1_out = A1L61 & A1L81 & !A1L71;
A1L42Q_or_out = A1L42Q_p1_out;
A1L42Q_reg_input = A1L42Q_or_out;
A1L42Q = DFFE(A1L42Q_reg_input, A1L51, , , );


--A1L7 is always1~5sexp at SEXP1
A1L7 = EXP(!Time_EN & !TimeSet_EN);


--clk_1khz is clk_1khz at PIN_43
--operation mode is input

clk_1khz = INPUT();


--clk_200hz is clk_200hz at PIN_12
--operation mode is input

clk_200hz = INPUT();


--Time_EN is Time_EN at PIN_24
--operation mode is input

Time_EN = INPUT();


--TimeSet_EN is TimeSet_EN at PIN_16
--operation mode is input

TimeSet_EN = INPUT();


--timeset_disp_drive[2] is timeset_disp_drive[2] at PIN_20
--operation mode is input

timeset_disp_drive[2] = INPUT();


--timeset_disp_drive[1] is timeset_disp_drive[1] at PIN_21
--operation mode is input

timeset_disp_drive[1] = INPUT();


--timeset_disp_drive[0] is timeset_disp_drive[0] at PIN_28
--operation mode is input

timeset_disp_drive[0] = INPUT();


--time_disp_select[5] is time_disp_select[5] at PIN_4
--operation mode is output

time_disp_select[5] = OUTPUT(A1L43Q);


--time_disp_select[4] is time_disp_select[4] at PIN_5
--operation mode is output

time_disp_select[4] = OUTPUT(A1L23Q);


--time_disp_select[3] is time_disp_select[3] at PIN_6
--operation mode is output

time_disp_select[3] = OUTPUT(A1L03Q);


--time_disp_select[2] is time_disp_select[2] at PIN_8
--operation mode is output

time_disp_select[2] = OUTPUT(A1L82Q);


--time_disp_select[1] is time_disp_select[1] at PIN_9
--operation mode is output

time_disp_select[1] = OUTPUT(A1L62Q);


--time_disp_select[0] is time_disp_select[0] at PIN_11
--operation mode is output

time_disp_select[0] = OUTPUT(A1L42Q);