time_disp_select.tan.qmsg

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "always1~5sexp " "Info: Detected gated clock \"always1~5sexp\" as buffer" {  } { { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "always1~5sexp" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "clk~24 " "Info: Detected gated clock \"clk~24\" as buffer" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 33 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "clk~24" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "clk~13 " "Info: Detected gated clock \"clk~13\" as buffer" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 33 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "clk~13" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_1khz register auto_disp_drive\[1\] register auto_disp_drive\[0\] 175.44 MHz 5.7 ns Internal " "Info: Clock \"clk_1khz\" has Internal fmax of 175.44 MHz between source register \"auto_disp_drive\[1\]\" and destination register \"auto_disp_drive\[0\]\" (period= 5.7 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.600 ns + Longest register register " "Info: + Longest register to register delay is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns auto_disp_drive\[1\] 1 REG LC16 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC16; Fanout = 6; REG Node = 'auto_disp_drive\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "" { auto_disp_drive[1] } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 28 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 3.600 ns auto_disp_drive\[0\] 2 REG LC11 7 " "Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC11; Fanout = 7; REG Node = 'auto_disp_drive\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "3.600 ns" { auto_disp_drive[1] auto_disp_drive[0] } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 28 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 72.22 % " "Info: Total cell delay = 2.600 ns ( 72.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 27.78 % " "Info: Total interconnect delay = 1.000 ns ( 27.78 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "3.600 ns" { auto_disp_drive[1] auto_disp_drive[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { auto_disp_drive[1] auto_disp_drive[0] } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_1khz destination 1.300 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_1khz\" to destination register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns clk_1khz 1 CLK PIN_43 4 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'clk_1khz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "" { clk_1khz } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns auto_disp_drive\[0\] 2 REG LC11 7 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC11; Fanout = 7; REG Node = 'auto_disp_drive\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "0.100 ns" { clk_1khz auto_disp_drive[0] } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 28 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "1.300 ns" { clk_1khz auto_disp_drive[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { clk_1khz clk_1khz~out auto_disp_drive[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_1khz source 1.300 ns - Longest register " "Info: - Longest clock path from clock \"clk_1khz\" to source register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns clk_1khz 1 CLK PIN_43 4 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'clk_1khz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "" { clk_1khz } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns auto_disp_drive\[1\] 2 REG LC16 6 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC16; Fanout = 6; REG Node = 'auto_disp_drive\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "0.100 ns" { clk_1khz auto_disp_drive[1] } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 28 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "1.300 ns" { clk_1khz auto_disp_drive[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { clk_1khz clk_1khz~out auto_disp_drive[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "1.300 ns" { clk_1khz auto_disp_drive[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { clk_1khz clk_1khz~out auto_disp_drive[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "1.300 ns" { clk_1khz auto_disp_drive[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { clk_1khz clk_1khz~out auto_disp_drive[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 28 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 28 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "3.600 ns" { auto_disp_drive[1] auto_disp_drive[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { auto_disp_drive[1] auto_disp_drive[0] } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "1.300 ns" { clk_1khz auto_disp_drive[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { clk_1khz clk_1khz~out auto_disp_drive[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "1.300 ns" { clk_1khz auto_disp_drive[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { clk_1khz clk_1khz~out auto_disp_drive[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "Time_EN " "Info: No valid register-to-register data paths exist for clock \"Time_EN\"" {  } {  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "clk_200hz " "Info: No valid register-to-register data paths exist for clock \"clk_200hz\"" {  } {  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "TimeSet_EN " "Info: No valid register-to-register data paths exist for clock \"TimeSet_EN\"" {  } {  } 0}