time_disp_select.tan.qmsg

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "disp_drive\[0\]~70 " "Info: Node \"disp_drive\[0\]~70\"" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 33 -1 0 } }  } 0}  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 33 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "disp_drive\[2\]~66 " "Info: Node \"disp_drive\[2\]~66\"" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 33 -1 0 } }  } 0}  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 33 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "disp_drive\[1\]~56 " "Info: Node \"disp_drive\[1\]~56\"" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 33 -1 0 } }  } 0}  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 33 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "clk~24 " "Info: Node \"clk~24\"" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 33 -1 0 } }  } 0}  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 33 -1 0 } }  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_1khz " "Info: Assuming node \"clk_1khz\" is an undefined clock" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 11 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "clk_1khz" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "Time_EN " "Info: Assuming node \"Time_EN\" is an undefined clock" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 13 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "Time_EN" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_200hz " "Info: Assuming node \"clk_200hz\" is an undefined clock" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 12 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "clk_200hz" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "TimeSet_EN " "Info: Assuming node \"TimeSet_EN\" is an undefined clock" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 14 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "TimeSet_EN" } } } }  } 0}  } {  } 0}