time_disp_select.hier_info

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

|time_disp_select
clk_1khz => auto_disp_drive[1].CLK
clk_1khz => auto_disp_drive[0].CLK
clk_1khz => clk~0.DATAB
clk_1khz => auto_disp_drive[2].CLK
clk_200hz => clk~0.DATAA
Time_EN => clk~0.OUTPUTSELECT
Time_EN => disp_drive~0.OUTPUTSELECT
Time_EN => disp_drive~1.OUTPUTSELECT
Time_EN => disp_drive~2.OUTPUTSELECT
Time_EN => always1~0.IN0
TimeSet_EN => always1~0.IN1
timeset_disp_drive[0] => disp_drive~2.DATAA
timeset_disp_drive[1] => disp_drive~1.DATAA
timeset_disp_drive[2] => disp_drive~0.DATAA
time_disp_select[0] <= time_disp_select[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
time_disp_select[1] <= time_disp_select[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
time_disp_select[2] <= time_disp_select[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
time_disp_select[3] <= time_disp_select[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
time_disp_select[4] <= time_disp_select[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
time_disp_select[5] <= time_disp_select[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE