time_disp_select.map.eqn

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

--auto_disp_drive[1] is auto_disp_drive[1]
auto_disp_drive[1]_p1_out = !auto_disp_drive[2] & auto_disp_drive[0] & !auto_disp_drive[1];
auto_disp_drive[1]_p2_out = !auto_disp_drive[2] & !auto_disp_drive[0] & auto_disp_drive[1];
auto_disp_drive[1]_or_out = auto_disp_drive[1]_p1_out # auto_disp_drive[1]_p2_out;
auto_disp_drive[1]_reg_input = auto_disp_drive[1]_or_out;
auto_disp_drive[1] = DFFE(auto_disp_drive[1]_reg_input, GLOBAL(clk_1khz), , , );


--A1L01 is clk~13
A1L01_p1_out = Time_EN & GLOBAL(clk_1khz);
A1L01_p2_out = !Time_EN & clk_200hz;
A1L01_or_out = A1L01_p1_out # A1L01_p2_out;
A1L01 = A1L01_or_out;


--A1L71 is disp_drive~43
A1L71_p1_out = Time_EN & auto_disp_drive[1];
A1L71_p2_out = !Time_EN & timeset_disp_drive[1];
A1L71_or_out = A1L71_p1_out # A1L71_p2_out;
A1L71 = A1L71_or_out;


--auto_disp_drive[2] is auto_disp_drive[2]
auto_disp_drive[2]_p1_out = !auto_disp_drive[0] & !auto_disp_drive[2];
auto_disp_drive[2]_p2_out = !auto_disp_drive[2] & !auto_disp_drive[1];
auto_disp_drive[2]_p3_out = !auto_disp_drive[0] & !auto_disp_drive[1];
auto_disp_drive[2]_or_out = auto_disp_drive[2]_p1_out # auto_disp_drive[2]_p2_out # auto_disp_drive[2]_p3_out;
auto_disp_drive[2]_reg_input = !auto_disp_drive[2]_or_out;
auto_disp_drive[2] = TFFE(auto_disp_drive[2]_reg_input, GLOBAL(clk_1khz), , , );


--A1L11 is clk~24
A1L11_p1_out = A1L01 & A1L3;
A1L11_p2_out = A1L11 & !Time_EN & !TimeSet_EN;
A1L11_p3_out = A1L01 & A1L11;
A1L11_or_out = A1L11_p1_out # A1L11_p2_out # A1L11_p3_out;
A1L11 = A1L11_or_out;


--A1L31 is disp_drive[1]~56
A1L31_p1_out = A1L71 & A1L3;
A1L31_p2_out = A1L31 & !Time_EN & !TimeSet_EN;
A1L31_p3_out = A1L71 & A1L31;
A1L31_or_out = A1L31_p1_out # A1L31_p2_out # A1L31_p3_out;
A1L31 = A1L31_or_out;


--auto_disp_drive[0] is auto_disp_drive[0]
auto_disp_drive[0]_p1_out = auto_disp_drive[2] & auto_disp_drive[1] & !auto_disp_drive[0];
auto_disp_drive[0]_or_out = auto_disp_drive[0]_p1_out;
auto_disp_drive[0]_reg_input = !auto_disp_drive[0]_or_out;
auto_disp_drive[0] = TFFE(auto_disp_drive[0]_reg_input, GLOBAL(clk_1khz), , , );


--A1L61 is disp_drive~41
A1L61_p1_out = Time_EN & auto_disp_drive[2];
A1L61_p2_out = !Time_EN & timeset_disp_drive[2];
A1L61_or_out = A1L61_p1_out # A1L61_p2_out;
A1L61 = A1L61_or_out;


--A1L51 is disp_drive~39
A1L51_p1_out = auto_disp_drive[0] & Time_EN;
A1L51_p2_out = !Time_EN & timeset_disp_drive[0];
A1L51_or_out = A1L51_p1_out # A1L51_p2_out;
A1L51 = A1L51_or_out;


--A1L41 is disp_drive[2]~66
A1L41_p1_out = A1L61 & A1L3;
A1L41_p2_out = A1L41 & !Time_EN & !TimeSet_EN;
A1L41_p3_out = A1L61 & A1L41;
A1L41_or_out = A1L41_p1_out # A1L41_p2_out # A1L41_p3_out;
A1L41 = A1L41_or_out;


--A1L21 is disp_drive[0]~70
A1L21_p1_out = A1L51 & A1L3;
A1L21_p2_out = A1L21 & !Time_EN & !TimeSet_EN;
A1L21_p3_out = A1L51 & A1L21;
A1L21_or_out = A1L21_p1_out # A1L21_p2_out # A1L21_p3_out;
A1L21 = A1L21_or_out;


--A1L03Q is time_disp_select[5]~reg0
A1L03Q_p1_out = !A1L21 & !A1L41 & !A1L31;
A1L03Q_or_out = A1L03Q_p1_out;
A1L03Q_reg_input = A1L03Q_or_out;
A1L03Q = DFFE(A1L03Q_reg_input, A1L11, , , );


--A1L82Q is time_disp_select[4]~reg0
A1L82Q_p1_out = A1L21 & !A1L41 & !A1L31;
A1L82Q_or_out = A1L82Q_p1_out;
A1L82Q_reg_input = A1L82Q_or_out;
A1L82Q = DFFE(A1L82Q_reg_input, A1L11, , , );


--A1L62Q is time_disp_select[3]~reg0
A1L62Q_p1_out = !A1L21 & !A1L41 & A1L31;
A1L62Q_or_out = A1L62Q_p1_out;
A1L62Q_reg_input = A1L62Q_or_out;
A1L62Q = DFFE(A1L62Q_reg_input, A1L11, , , );


--A1L42Q is time_disp_select[2]~reg0
A1L42Q_p1_out = A1L21 & !A1L41 & A1L31;
A1L42Q_or_out = A1L42Q_p1_out;
A1L42Q_reg_input = A1L42Q_or_out;
A1L42Q = DFFE(A1L42Q_reg_input, A1L11, , , );


--A1L22Q is time_disp_select[1]~reg0
A1L22Q_p1_out = !A1L21 & A1L41 & !A1L31;
A1L22Q_or_out = A1L22Q_p1_out;
A1L22Q_reg_input = A1L22Q_or_out;
A1L22Q = DFFE(A1L22Q_reg_input, A1L11, , , );


--A1L02Q is time_disp_select[0]~reg0
A1L02Q_p1_out = A1L21 & A1L41 & !A1L31;
A1L02Q_or_out = A1L02Q_p1_out;
A1L02Q_reg_input = A1L02Q_or_out;
A1L02Q = DFFE(A1L02Q_reg_input, A1L11, , , );


--A1L3 is always1~5sexp
A1L3 = EXP(!Time_EN & !TimeSet_EN);


--clk_1khz is clk_1khz
--operation mode is input

clk_1khz = INPUT();


--clk_200hz is clk_200hz
--operation mode is input

clk_200hz = INPUT();


--Time_EN is Time_EN
--operation mode is input

Time_EN = INPUT();


--TimeSet_EN is TimeSet_EN
--operation mode is input

TimeSet_EN = INPUT();


--timeset_disp_drive[2] is timeset_disp_drive[2]
--operation mode is input

timeset_disp_drive[2] = INPUT();


--timeset_disp_drive[1] is timeset_disp_drive[1]
--operation mode is input

timeset_disp_drive[1] = INPUT();


--timeset_disp_drive[0] is timeset_disp_drive[0]
--operation mode is input

timeset_disp_drive[0] = INPUT();


--time_disp_select[5] is time_disp_select[5]
--operation mode is output

time_disp_select[5] = OUTPUT(A1L03Q);


--time_disp_select[4] is time_disp_select[4]
--operation mode is output

time_disp_select[4] = OUTPUT(A1L82Q);


--time_disp_select[3] is time_disp_select[3]
--operation mode is output

time_disp_select[3] = OUTPUT(A1L62Q);


--time_disp_select[2] is time_disp_select[2]
--operation mode is output

time_disp_select[2] = OUTPUT(A1L42Q);


--time_disp_select[1] is time_disp_select[1]
--operation mode is output

time_disp_select[1] = OUTPUT(A1L22Q);


--time_disp_select[0] is time_disp_select[0]
--operation mode is output

time_disp_select[0] = OUTPUT(A1L02Q);