time_disp_select.tan.summary

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 5.400 ns
From           : Time_EN
To             : time_disp_select[0]~reg0
From Clock     : 
To Clock       : TimeSet_EN
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 14.700 ns
From           : time_disp_select[5]~reg0
To             : time_disp_select[5]
From Clock     : Time_EN
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 6.500 ns
From           : TimeSet_EN
To             : time_disp_select[0]~reg0
From Clock     : 
To Clock       : Time_EN
Failed Paths   : 0

Type           : Clock Setup: 'clk_1khz'
Slack          : N/A
Required Time  : None
Actual Time    : 175.44 MHz ( period = 5.700 ns )
From           : auto_disp_drive[0]
To             : auto_disp_drive[1]
From Clock     : clk_1khz
To Clock       : clk_1khz
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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