time_disp_select.v

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

module time_disp_select(
						clk_1khz,
						clk_200hz,
						Time_EN,
						TimeSet_EN,
						timeset_disp_drive,
						time_disp_select
						);
						
output [5:0] time_disp_select;
input  clk_1khz;
input  clk_200hz;
input  Time_EN;
input  TimeSet_EN;
input  [2:0] timeset_disp_drive;

reg [5:0] time_disp_select;
reg [2:0] auto_disp_drive;
reg clk;
reg [2:0] disp_drive;

always @(posedge clk_1khz)
begin  
  if(auto_disp_drive < 3'b101)
    auto_disp_drive <= auto_disp_drive + 3'b1;
  else
    auto_disp_drive <= 3'b0;
end


always
begin
  if(Time_EN == 1'b1)
  begin
    clk        <= clk_1khz;
    disp_drive <= auto_disp_drive;
  end
  else if(TimeSet_EN == 1'b1)
  begin  
    clk        <= clk_200hz;
    disp_drive <= timeset_disp_drive;
  end
end


always @(posedge clk)
begin
  case(disp_drive)
    3'b000:  time_disp_select <= 6'b100000;
    3'b001:  time_disp_select <= 6'b010000;
    3'b010:  time_disp_select <= 6'b001000;
    3'b011:  time_disp_select <= 6'b000100;
    3'b100:  time_disp_select <= 6'b000010;
    3'b101:  time_disp_select <= 6'b000001;
    default: time_disp_select <= 6'b000000;
  endcase
end

endmodule