time_disp_select.tan.rpt

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

; N/A           ; None        ; 1.800 ns  ; timeset_disp_drive[1] ; time_disp_select[2]~reg0 ; clk_200hz  ;
; N/A           ; None        ; 1.800 ns  ; timeset_disp_drive[1] ; time_disp_select[2]~reg0 ; clk_1khz   ;
; N/A           ; None        ; 1.800 ns  ; timeset_disp_drive[1] ; time_disp_select[1]~reg0 ; clk_200hz  ;
; N/A           ; None        ; 1.800 ns  ; timeset_disp_drive[1] ; time_disp_select[1]~reg0 ; clk_1khz   ;
; N/A           ; None        ; 1.800 ns  ; timeset_disp_drive[1] ; time_disp_select[0]~reg0 ; clk_200hz  ;
; N/A           ; None        ; 1.800 ns  ; timeset_disp_drive[1] ; time_disp_select[0]~reg0 ; clk_1khz   ;
; N/A           ; None        ; 0.300 ns  ; timeset_disp_drive[0] ; time_disp_select[5]~reg0 ; TimeSet_EN ;
; N/A           ; None        ; 0.300 ns  ; timeset_disp_drive[0] ; time_disp_select[4]~reg0 ; TimeSet_EN ;
; N/A           ; None        ; 0.300 ns  ; timeset_disp_drive[0] ; time_disp_select[3]~reg0 ; TimeSet_EN ;
; N/A           ; None        ; 0.300 ns  ; timeset_disp_drive[0] ; time_disp_select[2]~reg0 ; TimeSet_EN ;
; N/A           ; None        ; 0.300 ns  ; timeset_disp_drive[0] ; time_disp_select[1]~reg0 ; TimeSet_EN ;
; N/A           ; None        ; 0.300 ns  ; timeset_disp_drive[0] ; time_disp_select[0]~reg0 ; TimeSet_EN ;
; N/A           ; None        ; 0.300 ns  ; timeset_disp_drive[2] ; time_disp_select[5]~reg0 ; TimeSet_EN ;
; N/A           ; None        ; 0.300 ns  ; timeset_disp_drive[2] ; time_disp_select[4]~reg0 ; TimeSet_EN ;
; N/A           ; None        ; 0.300 ns  ; timeset_disp_drive[2] ; time_disp_select[3]~reg0 ; TimeSet_EN ;
; N/A           ; None        ; 0.300 ns  ; timeset_disp_drive[2] ; time_disp_select[2]~reg0 ; TimeSet_EN ;
; N/A           ; None        ; 0.300 ns  ; timeset_disp_drive[2] ; time_disp_select[1]~reg0 ; TimeSet_EN ;
; N/A           ; None        ; 0.300 ns  ; timeset_disp_drive[2] ; time_disp_select[0]~reg0 ; TimeSet_EN ;
; N/A           ; None        ; 0.300 ns  ; timeset_disp_drive[1] ; time_disp_select[5]~reg0 ; TimeSet_EN ;
; N/A           ; None        ; 0.300 ns  ; timeset_disp_drive[1] ; time_disp_select[4]~reg0 ; TimeSet_EN ;
; N/A           ; None        ; 0.300 ns  ; timeset_disp_drive[1] ; time_disp_select[3]~reg0 ; TimeSet_EN ;
; N/A           ; None        ; 0.300 ns  ; timeset_disp_drive[1] ; time_disp_select[2]~reg0 ; TimeSet_EN ;
; N/A           ; None        ; 0.300 ns  ; timeset_disp_drive[1] ; time_disp_select[1]~reg0 ; TimeSet_EN ;
; N/A           ; None        ; 0.300 ns  ; timeset_disp_drive[1] ; time_disp_select[0]~reg0 ; TimeSet_EN ;
+---------------+-------------+-----------+-----------------------+--------------------------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Sat Jul 15 21:02:17 2006
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off time_disp_select -c time_disp_select
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Found combinational loop of 1 nodes
    Info: Node "disp_drive[0]~70"
Info: Found combinational loop of 1 nodes
    Info: Node "disp_drive[2]~66"
Info: Found combinational loop of 1 nodes
    Info: Node "disp_drive[1]~56"
Info: Found combinational loop of 1 nodes
    Info: Node "clk~24"
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk_1khz" is an undefined clock
    Info: Assuming node "Time_EN" is an undefined clock
    Info: Assuming node "clk_200hz" is an undefined clock
    Info: Assuming node "TimeSet_EN" is an undefined clock
Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock "always1~5sexp" as buffer
    Info: Detected gated clock "clk~24" as buffer
    Info: Detected gated clock "clk~13" as buffer
Info: Clock "clk_1khz" has Internal fmax of 175.44 MHz between source register "auto_disp_drive[1]" and destination register "auto_disp_drive[0]" (period= 5.7 ns)
    Info: + Longest register to register delay is 3.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC16; Fanout = 6; REG Node = 'auto_disp_drive[1]'
        Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC11; Fanout = 7; REG Node = 'auto_disp_drive[0]'
        Info: Total cell delay = 2.600 ns ( 72.22 % )
        Info: Total interconnect delay = 1.000 ns ( 27.78 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk_1khz" to destination register is 1.300 ns
            Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'clk_1khz'
            Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC11; Fanout = 7; REG Node = 'auto_disp_drive[0]'
            Info: Total cell delay = 1.300 ns ( 100.00 % )
        Info: - Longest clock path from clock "clk_1khz" to source register is 1.300 ns
            Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'clk_1khz'
            Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC16; Fanout = 6; REG Node = 'auto_disp_drive[1]'
            Info: Total cell delay = 1.300 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.300 ns
    Info: + Micro setup delay of destination is 0.800 ns
Info: No valid register-to-register data paths exist for clock "Time_EN"
Info: No valid register-to-register data paths exist for clock "clk_200hz"
Info: No valid register-to-register data paths exist for clock "TimeSet_EN"
Info: tsu for register "time_disp_select[5]~reg0" (data pin = "Time_EN", clock pin = "TimeSet_EN") is 5.400 ns
    Info: + Longest pin to register delay is 13.100 ns
        Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_24; Fanout = 17; CLK Node = 'Time_EN'
        Info: 2: + IC(1.100 ns) + CELL(3.600 ns) = 4.900 ns; Loc. = LC9; Fanout = 3; COMB Node = 'disp_drive~39'
        Info: 3: + IC(0.000 ns) + CELL(4.600 ns) = 9.500 ns; Loc. = LC4; Fanout = 8; COMB LOOP Node = 'disp_drive[0]~70'
            Info: Loc. = LC4; Node "disp_drive[0]~70"
        Info: 4: + IC(1.000 ns) + CELL(2.600 ns) = 13.100 ns; Loc. = LC1; Fanout = 1; REG Node = 'time_disp_select[5]~reg0'
        Info: Total cell delay = 11.000 ns ( 83.97 % )
        Info: Total interconnect delay = 2.100 ns ( 16.03 % )
    Info: + Micro setup delay of destination is 0.800 ns
    Info: - Shortest clock path from clock "TimeSet_EN" to destination register is 8.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_16; Fanout = 9; CLK Node = 'TimeSet_EN'
        Info: 2: + IC(0.000 ns) + CELL(4.600 ns) = 4.800 ns; Loc. = LC13; Fanout = 8; COMB LOOP Node = 'clk~24'
            Info: Loc. = LC13; Node "clk~24"
        Info: 3: + IC(1.000 ns) + CELL(2.700 ns) = 8.500 ns; Loc. = LC1; Fanout = 1; REG Node = 'time_disp_select[5]~reg0'
        Info: Total cell delay = 7.500 ns ( 88.24 % )
        Info: Total interconnect delay = 1.000 ns ( 11.76 % )
Info: tco from clock "Time_EN" to destination pin "time_disp_select[0]" through register "time_disp_select[0]~reg0" is 14.700 ns
    Info: + Longest clock path from clock "Time_EN" to source register is 13.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_24; Fanout = 17; CLK Node = 'Time_EN'
        Info: 2: + IC(1.100 ns) + CELL(3.600 ns) = 4.900 ns; Loc. = LC25; Fanout = 3; COMB Node = 'clk~13'
        Info: 3: + IC(0.000 ns) + CELL(4.600 ns) = 9.500 ns; Loc. = LC13; Fanout = 8; COMB LOOP Node = 'clk~24'
            Info: Loc. = LC13; Node "clk~24"
        Info: 4: + IC(1.000 ns) + CELL(2.700 ns) = 13.200 ns; Loc. = LC7; Fanout = 1; REG Node = 'time_disp_select[0]~reg0'
        Info: Total cell delay = 11.100 ns ( 84.09 % )
        Info: Total interconnect delay = 2.100 ns ( 15.91 % )
    Info: + Micro clock to output delay of source is 1.300 ns
    Info: + Longest register to pin delay is 0.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7; Fanout = 1; REG Node = 'time_disp_select[0]~reg0'
        Info: 2: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'time_disp_select[0]'
        Info: Total cell delay = 0.200 ns ( 100.00 % )
Info: th for register "time_disp_select[5]~reg0" (data pin = "TimeSet_EN", clock pin = "Time_EN") is 6.500 ns
    Info: + Longest clock path from clock "Time_EN" to destination register is 13.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_24; Fanout = 17; CLK Node = 'Time_EN'
        Info: 2: + IC(1.100 ns) + CELL(3.600 ns) = 4.900 ns; Loc. = LC25; Fanout = 3; COMB Node = 'clk~13'
        Info: 3: + IC(0.000 ns) + CELL(4.600 ns) = 9.500 ns; Loc. = LC13; Fanout = 8; COMB LOOP Node = 'clk~24'
            Info: Loc. = LC13; Node "clk~24"
        Info: 4: + IC(1.000 ns) + CELL(2.700 ns) = 13.200 ns; Loc. = LC1; Fanout = 1; REG Node = 'time_disp_select[5]~reg0'
        Info: Total cell delay = 11.100 ns ( 84.09 % )
        Info: Total interconnect delay = 2.100 ns ( 15.91 % )
    Info: + Micro hold delay of destination is 1.700 ns
    Info: - Shortest pin to register delay is 8.400 ns
        Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_16; Fanout = 9; CLK Node = 'TimeSet_EN'
        Info: 2: + IC(0.000 ns) + CELL(4.600 ns) = 4.800 ns; Loc. = LC4; Fanout = 8; COMB LOOP Node = 'disp_drive[0]~70'
            Info: Loc. = LC4; Node "disp_drive[0]~70"
        Info: 3: + IC(1.000 ns) + CELL(2.600 ns) = 8.400 ns; Loc. = LC1; Fanout = 1; REG Node = 'time_disp_select[5]~reg0'
        Info: Total cell delay = 7.400 ns ( 88.10 % )
        Info: Total interconnect delay = 1.000 ns ( 11.90 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Sat Jul 15 21:02:18 2006
    Info: Elapsed time: 00:00:02