date_main.map.qmsg

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 13 20:28:46 2006 " "Info: Processing started: Thu Jul 13 20:28:46 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off date_main -c date_main --convert_bdf_to_verilog=date_main.bdf " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off date_main -c date_main --convert_bdf_to_verilog=date_main.bdf" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "date_main.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file date_main.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 date_main " "Info: Found entity 1: date_main" {  } { { "date_main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/date_main.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 13 20:28:46 2006 " "Info: Processing ended: Thu Jul 13 20:28:46 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:0