date_main.tan.qmsg

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "day_EN " "Info: Assuming node \"day_EN\" is an undefined clock" {  } { { "date_main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/date_main.bdf" { { 88 -80 88 104 "day_EN" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "day_EN" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "SW1 " "Info: Assuming node \"SW1\" is an undefined clock" {  } { { "date_main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/date_main.bdf" { { 248 -80 88 264 "SW1" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "SW1" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "SW2 " "Info: Assuming node \"SW2\" is an undefined clock" {  } { { "date_main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/date_main.bdf" { { 264 -80 88 280 "SW2" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "SW2" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "date_disp_clk " "Info: Assuming node \"date_disp_clk\" is an undefined clock" {  } { { "date_main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/date_main.bdf" { { 48 -80 88 64 "date_disp_clk" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "date_disp_clk" } } } }  } 0}  } {  } 0}