date_main.asm.qmsg

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 13 20:22:02 2006 " "Info: Processing started: Thu Jul 13 20:22:02 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --import_settings_files=off --export_settings_files=off date_main -c date_main " "Info: Command: quartus_asm --import_settings_files=off --export_settings_files=off date_main -c date_main" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 13 20:22:02 2006 " "Info: Processing ended: Thu Jul 13 20:22:02 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}