datecontrol.v

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

module datecontrol(clk,
                   Date_EN,
                   EN1,auto_month1,auto_month0,auto_day1,auto_day0,
                   EN2,set_month1,set_month0,set_day1,set_day0,disp_drive,
                   month1,month0,day1,day0,disp_select);

output [3:0] month1,month0,day1,day0;
output [5:0] disp_select;
input  clk,Date_EN;
input  EN1,EN2;
input  [3:0] auto_month1,auto_month0,auto_day1,auto_day0;
input  [3:0] set_month1,set_month0,set_day1,set_day0;
input  [1:0] disp_drive;

reg [3:0] month1,month0,day1,day0;
reg [5:0] disp_select;
reg [1:0] auto_disp_drive;

always @(posedge clk)
begin
  if((EN1 == 1'b1)&&(Date_EN == 1'b1))
  begin
    month1 <= auto_month1;
    month0 <= auto_month0;
    day1   <= auto_day1;
    day0   <= auto_day0;
    if(auto_disp_drive != 2'b11)
	  auto_disp_drive = auto_disp_drive + 2'b1;
	case(auto_disp_drive)
	  2'b00:   disp_select <= 6'b100000;
	  2'b01:   disp_select <= 6'b010000;
	  2'b10:   disp_select <= 6'b001000;
	  2'b11:   disp_select <= 6'b000100;
	  default: disp_select <= 6'b000000;
	endcase
  end
  else if(EN2 == 1'b1)
  begin
    month1 <= set_month1;
    month0 <= set_month0;
    day1   <= set_day1;
    day0   <= set_day0;
    case(disp_drive)
	  2'b00:   disp_select <= 6'b100000;
	  2'b01:   disp_select <= 6'b010000;
	  2'b10:   disp_select <= 6'b001000;
	  2'b11:   disp_select <= 6'b000100;
	  default: disp_select <= 6'b000000;
	endcase
  end
end
endmodule