date_main.v

来自「基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码」· Verilog 代码 · 共 73 行

// Copyright (C) 1991-2004 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
// a separate agreement with  Altera  or a megafunction partner.  Title to the
// intellectual property,  including patents,  copyrights,  trademarks,  trade
// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
// related documentation or information provided by  Altera  or a megafunction
// partner, remains with Altera, the megafunction partner, or their respective
// licensors. No other licenses, including any licenses needed under any third
// party's intellectual property, are provided herein.

module date_main(
	day_EN,
	date_disp_clk,
	Date_Set_EN,
	Date_EN,
	SW1,
	SW2,
	day0,
	day1,
	Disp_select_date,
	month0,
	month1
);

input	day_EN;
input	date_disp_clk;
input	Date_Set_EN;
input	Date_EN;
input	SW1;
input	SW2;
output	[3:0] day0;
output	[3:0] day1;
output	[5:0] Disp_select_date;
output	[3:0] month0;
output	[3:0] month1;

wire	SYNTHESIZED_WIRE_0;
wire	[3:0] SYNTHESIZED_WIRE_1;
wire	[3:0] SYNTHESIZED_WIRE_2;
wire	[3:0] SYNTHESIZED_WIRE_3;
wire	[3:0] SYNTHESIZED_WIRE_4;
wire	[1:0] SYNTHESIZED_WIRE_5;
wire	[3:0] SYNTHESIZED_WIRE_6;
wire	[3:0] SYNTHESIZED_WIRE_7;
wire	[3:0] SYNTHESIZED_WIRE_8;
wire	[3:0] SYNTHESIZED_WIRE_9;





autodate	b2v_inst(.EN1(day_EN),
.EN2(Date_Set_EN),.EO1(SYNTHESIZED_WIRE_0),.day0(SYNTHESIZED_WIRE_1),.day1(SYNTHESIZED_WIRE_2),.month0(SYNTHESIZED_WIRE_3),.month1(SYNTHESIZED_WIRE_4));

datecontrol	b2v_inst1(.clk(date_disp_clk),
.Date_EN(Date_EN),.EN1(SYNTHESIZED_WIRE_0),.EN2(Date_Set_EN),.auto_day0(SYNTHESIZED_WIRE_1),.auto_day1(SYNTHESIZED_WIRE_2),.auto_month0(SYNTHESIZED_WIRE_3),.auto_month1(SYNTHESIZED_WIRE_4),.disp_drive(SYNTHESIZED_WIRE_5),.set_day0(SYNTHESIZED_WIRE_6),.set_day1(SYNTHESIZED_WIRE_7),.set_month0(SYNTHESIZED_WIRE_8),.set_month1(SYNTHESIZED_WIRE_9),.day0(day0),.day1(day1),.disp_select(Disp_select_date),.month0(month0),.month1(month1));

setdate	b2v_inst2(.EN2(Date_Set_EN),
.SW1(SW1),.SW2(SW2),.day_set0(SYNTHESIZED_WIRE_6),.day_set1(SYNTHESIZED_WIRE_7),.disp_drive(SYNTHESIZED_WIRE_5),.month_set0(SYNTHESIZED_WIRE_8),.month_set1(SYNTHESIZED_WIRE_9));


endmodule