date_main.map.rpt

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

;    |datecontrol:inst1|               ; 16         ; 0    ; |date_main|datecontrol:inst1                          ;
;    |setdate:inst2|                   ; 14         ; 0    ; |date_main|setdate:inst2                              ;
;       |lpm_counter:day_set0_rtl_0|   ; 4          ; 0    ; |date_main|setdate:inst2|lpm_counter:day_set0_rtl_0   ;
;       |lpm_counter:day_set1_rtl_2|   ; 2          ; 0    ; |date_main|setdate:inst2|lpm_counter:day_set1_rtl_2   ;
;       |lpm_counter:month_set0_rtl_4| ; 4          ; 0    ; |date_main|setdate:inst2|lpm_counter:month_set0_rtl_4 ;
;       |lpm_counter:month_set1_rtl_5| ; 2          ; 0    ; |date_main|setdate:inst2|lpm_counter:month_set1_rtl_5 ;
+--------------------------------------+------------+------+-------------------------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/date_main.map.eqn.


+------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                       ;
+----------------------------------+-----------------+-------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Name with Absolute Path                                            ;
+----------------------------------+-----------------+-------------------------------------------------------------------------+
; date_main.bdf                    ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/date_main.bdf ;
; datecontrol.v                    ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/datecontrol.v ;
; autodate.v                       ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/autodate.v    ;
; setdate.v                        ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/setdate.v     ;
; lpm_counter.tdf                  ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf             ;
; lpm_constant.inc                 ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_constant.inc            ;
; lpm_decode.inc                   ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_decode.inc              ;
; lpm_add_sub.inc                  ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_add_sub.inc             ;
; cmpconst.inc                     ; yes             ; d:/altera/quartus42/libraries/megafunctions/cmpconst.inc                ;
; lpm_compare.inc                  ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_compare.inc             ;
; lpm_counter.inc                  ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_counter.inc             ;
; dffeea.inc                       ; yes             ; d:/altera/quartus42/libraries/megafunctions/dffeea.inc                  ;
; alt_synch_counter.inc            ; yes             ; d:/altera/quartus42/libraries/megafunctions/alt_synch_counter.inc       ;
; alt_synch_counter_f.inc          ; yes             ; d:/altera/quartus42/libraries/megafunctions/alt_synch_counter_f.inc     ;
; alt_counter_f10ke.inc            ; yes             ; d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.inc       ;
; alt_counter_stratix.inc          ; yes             ; d:/altera/quartus42/libraries/megafunctions/alt_counter_stratix.inc     ;
; aglobal42.inc                    ; yes             ; d:/altera/quartus42/libraries/megafunctions/aglobal42.inc               ;
+----------------------------------+-----------------+-------------------------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource             ; Usage                ;
+----------------------+----------------------+
; Logic cells          ; 61                   ;
; Total registers      ; 42                   ;
; I/O pins             ; 28                   ;
; Shareable expanders  ; 7                    ;
; Parallel expanders   ; 13                   ;
; Maximum fan-out node ; Date_Set_EN          ;
; Maximum fan-out      ; 33                   ;
; Total fan-out        ; 494                  ;
; Average fan-out      ; 5.15                 ;
+----------------------+----------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Thu Jul 13 20:21:36 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off date_main -c date_main
Warning: Can't analyze file -- file E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/date_main/date_main.v is missing
Info: Found 1 design units, including 1 entities, in source file date_main.bdf
    Info: Found entity 1: date_main
Info: Using design file datecontrol.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: datecontrol
Info: Using design file autodate.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: autodate
Info: Using design file setdate.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: setdate
Warning: Reduced register "datecontrol:inst1|disp_select[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "datecontrol:inst1|disp_select[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "autodate:inst|month1[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "autodate:inst|month1[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "autodate:inst|month1[1]" with stuck data_in port to stuck value GND
Info: Inferred 6 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "setdate:inst2|day_set0[0]~8"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "autodate:inst|day1[0]~112"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "setdate:inst2|day_set1[0]~8"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "autodate:inst|month0[0]~118"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "setdate:inst2|month_set0[0]~8"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "setdate:inst2|month_set1[0]~8"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Warning: Reduced register "setdate:inst2|lpm_counter:day_set1_rtl_2|dffs[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "setdate:inst2|lpm_counter:day_set1_rtl_2|dffs[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "setdate:inst2|lpm_counter:month_set1_rtl_5|dffs[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "setdate:inst2|lpm_counter:month_set1_rtl_5|dffs[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "autodate:inst|lpm_counter:day1_rtl_1|dffs[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "autodate:inst|lpm_counter:day1_rtl_1|dffs[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "datecontrol:inst1|day1[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "datecontrol:inst1|day1[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "datecontrol:inst1|month1[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "datecontrol:inst1|month1[2]" with stuck data_in port to stuck value GND
Info: Power-up level of register "datecontrol:inst1|auto_disp_drive[1]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "datecontrol:inst1|auto_disp_drive[1]" with stuck data_in port to stuck value VCC
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "day1[3]" stuck at GND
    Warning: Pin "day1[2]" stuck at GND
    Warning: Pin "Disp_select_date[1]" stuck at GND
    Warning: Pin "Disp_select_date[0]" stuck at GND
    Warning: Pin "month1[3]" stuck at GND
    Warning: Pin "month1[2]" stuck at GND
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "date_disp_clk" to global clock signal
    Info: Promoted clock signal driven by pin "day_EN" to global clock signal
Info: Implemented 96 device resources after synthesis - the final resource count might be different
    Info: Implemented 6 input pins
    Info: Implemented 22 output pins
    Info: Implemented 61 macrocells
    Info: Implemented 7 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 24 warnings
    Info: Processing ended: Thu Jul 13 20:21:47 2006
    Info: Elapsed time: 00:00:12