autodate.tan.qmsg

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "EN1 " "Info: Assuming node \"EN1\" is an undefined clock" {  } { { "autodate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/autodate.v" 5 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "EN1" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "EN1 register lpm_counter:month0_rtl_0\|dffs\[1\] register lpm_counter:month0_rtl_0\|dffs\[0\] 112.36 MHz 8.9 ns Internal " "Info: Clock \"EN1\" has Internal fmax of 112.36 MHz between source register \"lpm_counter:month0_rtl_0\|dffs\[1\]\" and destination register \"lpm_counter:month0_rtl_0\|dffs\[0\]\" (period= 8.9 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.800 ns + Longest register register " "Info: + Longest register to register delay is 6.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:month0_rtl_0\|dffs\[1\] 1 REG LC16 47 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC16; Fanout = 47; REG Node = 'lpm_counter:month0_rtl_0\|dffs\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "" { lpm_counter:month0_rtl_0|dffs[1] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(3.100 ns) 4.200 ns lpm_counter:month0_rtl_0\|dffs\[0\]~287 2 COMB SEXP28 1 " "Info: 2: + IC(1.100 ns) + CELL(3.100 ns) = 4.200 ns; Loc. = SEXP28; Fanout = 1; COMB Node = 'lpm_counter:month0_rtl_0\|dffs\[0\]~287'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "4.200 ns" { lpm_counter:month0_rtl_0|dffs[1] lpm_counter:month0_rtl_0|dffs[0]~287 } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.600 ns) 6.800 ns lpm_counter:month0_rtl_0\|dffs\[0\] 3 REG LC21 48 " "Info: 3: + IC(0.000 ns) + CELL(2.600 ns) = 6.800 ns; Loc. = LC21; Fanout = 48; REG Node = 'lpm_counter:month0_rtl_0\|dffs\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "2.600 ns" { lpm_counter:month0_rtl_0|dffs[0]~287 lpm_counter:month0_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.700 ns 83.82 % " "Info: Total cell delay = 5.700 ns ( 83.82 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.100 ns 16.18 % " "Info: Total interconnect delay = 1.100 ns ( 16.18 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "6.800 ns" { lpm_counter:month0_rtl_0|dffs[1] lpm_counter:month0_rtl_0|dffs[0]~287 lpm_counter:month0_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.800 ns" { lpm_counter:month0_rtl_0|dffs[1] lpm_counter:month0_rtl_0|dffs[0]~287 lpm_counter:month0_rtl_0|dffs[0] } { 0.000ns 1.100ns 0.000ns } { 0.000ns 3.100ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "EN1 destination 1.300 ns + Shortest register " "Info: + Shortest clock path from clock \"EN1\" to destination register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns EN1 1 CLK PIN_43 12 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 12; CLK Node = 'EN1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "" { EN1 } "NODE_NAME" } "" } } { "autodate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/autodate.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns lpm_counter:month0_rtl_0\|dffs\[0\] 2 REG LC21 48 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC21; Fanout = 48; REG Node = 'lpm_counter:month0_rtl_0\|dffs\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "0.100 ns" { EN1 lpm_counter:month0_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "1.300 ns" { EN1 lpm_counter:month0_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { EN1 EN1~out lpm_counter:month0_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "EN1 source 1.300 ns - Longest register " "Info: - Longest clock path from clock \"EN1\" to source register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns EN1 1 CLK PIN_43 12 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 12; CLK Node = 'EN1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "" { EN1 } "NODE_NAME" } "" } } { "autodate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/autodate.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns lpm_counter:month0_rtl_0\|dffs\[1\] 2 REG LC16 47 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC16; Fanout = 47; REG Node = 'lpm_counter:month0_rtl_0\|dffs\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "0.100 ns" { EN1 lpm_counter:month0_rtl_0|dffs[1] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "1.300 ns" { EN1 lpm_counter:month0_rtl_0|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { EN1 EN1~out lpm_counter:month0_rtl_0|dffs[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "1.300 ns" { EN1 lpm_counter:month0_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { EN1 EN1~out lpm_counter:month0_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "1.300 ns" { EN1 lpm_counter:month0_rtl_0|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { EN1 EN1~out lpm_counter:month0_rtl_0|dffs[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "6.800 ns" { lpm_counter:month0_rtl_0|dffs[1] lpm_counter:month0_rtl_0|dffs[0]~287 lpm_counter:month0_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.800 ns" { lpm_counter:month0_rtl_0|dffs[1] lpm_counter:month0_rtl_0|dffs[0]~287 lpm_counter:month0_rtl_0|dffs[0] } { 0.000ns 1.100ns 0.000ns } { 0.000ns 3.100ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "1.300 ns" { EN1 lpm_counter:month0_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { EN1 EN1~out lpm_counter:month0_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "1.300 ns" { EN1 lpm_counter:month0_rtl_0|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { EN1 EN1~out lpm_counter:month0_rtl_0|dffs[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "lpm_counter:month0_rtl_0\|dffs\[1\] EN2 EN1 4.300 ns register " "Info: tsu for register \"lpm_counter:month0_rtl_0\|dffs\[1\]\" (data pin = \"EN2\", clock pin = \"EN1\") is 4.300 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.800 ns + Longest pin register " "Info: + Longest pin to register delay is 4.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns EN2 1 PIN PIN_44 31 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_44; Fanout = 31; PIN Node = 'EN2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "" { EN2 } "NODE_NAME" } "" } } { "autodate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/autodate.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(2.600 ns) 3.900 ns lpm_counter:month0_rtl_0\|dffs\[1\]~299 2 COMB LC15 1 " "Info: 2: + IC(0.100 ns) + CELL(2.600 ns) = 3.900 ns; Loc. = LC15; Fanout = 1; COMB Node = 'lpm_counter:month0_rtl_0\|dffs\[1\]~299'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "2.700 ns" { EN2 lpm_counter:month0_rtl_0|dffs[1]~299 } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 4.800 ns lpm_counter:month0_rtl_0\|dffs\[1\] 3 REG LC16 47 " "Info: 3: + IC(0.000 ns) + CELL(0.900 ns) = 4.800 ns; Loc. = LC16; Fanout = 47; REG Node = 'lpm_counter:month0_rtl_0\|dffs\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "0.900 ns" { lpm_counter:month0_rtl_0|dffs[1]~299 lpm_counter:month0_rtl_0|dffs[1] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.700 ns 97.92 % " "Info: Total cell delay = 4.700 ns ( 97.92 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.100 ns 2.08 % " "Info: Total interconnect delay = 0.100 ns ( 2.08 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "4.800 ns" { EN2 lpm_counter:month0_rtl_0|dffs[1]~299 lpm_counter:month0_rtl_0|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.800 ns" { EN2 EN2~out lpm_counter:month0_rtl_0|dffs[1]~299 lpm_counter:month0_rtl_0|dffs[1] } { 0.000ns 0.000ns 0.100ns 0.000ns } { 0.000ns 1.200ns 2.600ns 0.900ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "EN1 destination 1.300 ns - Shortest register " "Info: - Shortest clock path from clock \"EN1\" to destination register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns EN1 1 CLK PIN_43 12 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 12; CLK Node = 'EN1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "" { EN1 } "NODE_NAME" } "" } } { "autodate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/autodate.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns lpm_counter:month0_rtl_0\|dffs\[1\] 2 REG LC16 47 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC16; Fanout = 47; REG Node = 'lpm_counter:month0_rtl_0\|dffs\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "0.100 ns" { EN1 lpm_counter:month0_rtl_0|dffs[1] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "1.300 ns" { EN1 lpm_counter:month0_rtl_0|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { EN1 EN1~out lpm_counter:month0_rtl_0|dffs[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "4.800 ns" { EN2 lpm_counter:month0_rtl_0|dffs[1]~299 lpm_counter:month0_rtl_0|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.800 ns" { EN2 EN2~out lpm_counter:month0_rtl_0|dffs[1]~299 lpm_counter:month0_rtl_0|dffs[1] } { 0.000ns 0.000ns 0.100ns 0.000ns } { 0.000ns 1.200ns 2.600ns 0.900ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate_cmp.qrpt" Compiler "autodate" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/db/autodate.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/autodate/" "" "1.300 ns" { EN1 lpm_counter:month0_rtl_0|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { EN1 EN1~out lpm_counter:month0_rtl_0|dffs[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0}