autodate.tan.summary

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.300 ns
From           : EN2
To             : lpm_counter:month0_rtl_0|dffs[0]
From Clock     : 
To Clock       : EN1
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 2.800 ns
From           : EO1~reg0
To             : EO1
From Clock     : EN1
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -0.900 ns
From           : EN2
To             : lpm_counter:month0_rtl_0|dffs[0]
From Clock     : 
To Clock       : EN1
Failed Paths   : 0

Type           : Clock Setup: 'EN1'
Slack          : N/A
Required Time  : None
Actual Time    : 112.36 MHz ( period = 8.900 ns )
From           : lpm_counter:month0_rtl_0|dffs[0]
To             : lpm_counter:day0_rtl_2|dffs[3]
From Clock     : EN1
To Clock       : EN1
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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