datecontrol.tan.qmsg

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

{ "Info" "ITDB_FULL_TCO_RESULT" "clk disp_select\[2\] disp_select\[2\]~reg0 3.200 ns register " "Info: tco from clock \"clk\" to destination pin \"disp_select\[2\]\" through register \"disp_select\[2\]~reg0\" is 3.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.800 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clk 1 CLK PIN_87 20 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_87; Fanout = 20; CLK Node = 'clk'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "" { clk } "NODE_NAME" } "" } } { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/datecontrol.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 1.800 ns disp_select\[2\]~reg0 2 REG LC3 2 " "Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC3; Fanout = 2; REG Node = 'disp_select\[2\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "0.500 ns" { clk disp_select[2]~reg0 } "NODE_NAME" } "" } } { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/datecontrol.v" 51 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.800 ns 100.00 % " "Info: Total cell delay = 1.800 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "1.800 ns" { clk disp_select[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { clk clk~out disp_select[2]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.200 ns + " "Info: + Micro clock to output delay of source is 1.200 ns" {  } { { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/datecontrol.v" 51 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.200 ns + Longest register pin " "Info: + Longest register to pin delay is 0.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns disp_select\[2\]~reg0 1 REG LC3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 2; REG Node = 'disp_select\[2\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "" { disp_select[2]~reg0 } "NODE_NAME" } "" } } { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/datecontrol.v" 51 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns disp_select\[2\] 2 PIN PIN_12 0 " "Info: 2: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_12; Fanout = 0; PIN Node = 'disp_select\[2\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "0.200 ns" { disp_select[2]~reg0 disp_select[2] } "NODE_NAME" } "" } } { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/datecontrol.v" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.200 ns 100.00 % " "Info: Total cell delay = 0.200 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "0.200 ns" { disp_select[2]~reg0 disp_select[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "0.200 ns" { disp_select[2]~reg0 disp_select[2] } { 0.000ns 0.000ns } { 0.000ns 0.200ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "1.800 ns" { clk disp_select[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { clk clk~out disp_select[2]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "0.200 ns" { disp_select[2]~reg0 disp_select[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "0.200 ns" { disp_select[2]~reg0 disp_select[2] } { 0.000ns 0.000ns } { 0.000ns 0.200ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "month1\[3\]~reg0 set_month1\[3\] clk -0.400 ns register " "Info: th for register \"month1\[3\]~reg0\" (data pin = \"set_month1\[3\]\", clock pin = \"clk\") is -0.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.800 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clk 1 CLK PIN_87 20 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_87; Fanout = 20; CLK Node = 'clk'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "" { clk } "NODE_NAME" } "" } } { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/datecontrol.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 1.800 ns month1\[3\]~reg0 2 REG LC33 3 " "Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC33; Fanout = 3; REG Node = 'month1\[3\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "0.500 ns" { clk month1[3]~reg0 } "NODE_NAME" } "" } } { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/datecontrol.v" 51 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.800 ns 100.00 % " "Info: Total cell delay = 1.800 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "1.800 ns" { clk month1[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { clk clk~out month1[3]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.700 ns + " "Info: + Micro hold delay of destination is 1.700 ns" {  } { { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/datecontrol.v" 51 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.900 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns set_month1\[3\] 1 PIN PIN_57 2 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_57; Fanout = 2; PIN Node = 'set_month1\[3\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "" { set_month1[3] } "NODE_NAME" } "" } } { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/datecontrol.v" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.600 ns) 3.900 ns month1\[3\]~reg0 2 REG LC33 3 " "Info: 2: + IC(1.100 ns) + CELL(2.600 ns) = 3.900 ns; Loc. = LC33; Fanout = 3; REG Node = 'month1\[3\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "3.700 ns" { set_month1[3] month1[3]~reg0 } "NODE_NAME" } "" } } { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/datecontrol.v" 51 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 71.79 % " "Info: Total cell delay = 2.800 ns ( 71.79 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.100 ns 28.21 % " "Info: Total interconnect delay = 1.100 ns ( 28.21 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "3.900 ns" { set_month1[3] month1[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { set_month1[3] set_month1[3]~out month1[3]~reg0 } { 0.000ns 0.000ns 1.100ns } { 0.000ns 0.200ns 2.600ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "1.800 ns" { clk month1[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { clk clk~out month1[3]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "3.900 ns" { set_month1[3] month1[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { set_month1[3] set_month1[3]~out month1[3]~reg0 } { 0.000ns 0.000ns 1.100ns } { 0.000ns 0.200ns 2.600ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 13 20:12:47 2006 " "Info: Processing ended: Thu Jul 13 20:12:47 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}