datecontrol.tan.qmsg

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/datecontrol.v" 9 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register disp_select\[2\]~reg0 register disp_select\[2\]~reg0 175.44 MHz 5.7 ns Internal " "Info: Clock \"clk\" has Internal fmax of 175.44 MHz between source register \"disp_select\[2\]~reg0\" and destination register \"disp_select\[2\]~reg0\" (period= 5.7 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.700 ns + Longest register register " "Info: + Longest register to register delay is 3.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns disp_select\[2\]~reg0 1 REG LC3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 2; REG Node = 'disp_select\[2\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "" { disp_select[2]~reg0 } "NODE_NAME" } "" } } { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/datecontrol.v" 51 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.600 ns) 3.700 ns disp_select\[2\]~reg0 2 REG LC3 2 " "Info: 2: + IC(1.100 ns) + CELL(2.600 ns) = 3.700 ns; Loc. = LC3; Fanout = 2; REG Node = 'disp_select\[2\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "3.700 ns" { disp_select[2]~reg0 disp_select[2]~reg0 } "NODE_NAME" } "" } } { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/datecontrol.v" 51 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 70.27 % " "Info: Total cell delay = 2.600 ns ( 70.27 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.100 ns 29.73 % " "Info: Total interconnect delay = 1.100 ns ( 29.73 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "3.700 ns" { disp_select[2]~reg0 disp_select[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.700 ns" { disp_select[2]~reg0 disp_select[2]~reg0 } { 0.000ns 1.100ns } { 0.000ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.800 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clk 1 CLK PIN_87 20 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_87; Fanout = 20; CLK Node = 'clk'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "" { clk } "NODE_NAME" } "" } } { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/datecontrol.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 1.800 ns disp_select\[2\]~reg0 2 REG LC3 2 " "Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC3; Fanout = 2; REG Node = 'disp_select\[2\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "0.500 ns" { clk disp_select[2]~reg0 } "NODE_NAME" } "" } } { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/datecontrol.v" 51 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.800 ns 100.00 % " "Info: Total cell delay = 1.800 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "1.800 ns" { clk disp_select[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { clk clk~out disp_select[2]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.800 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clk 1 CLK PIN_87 20 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_87; Fanout = 20; CLK Node = 'clk'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "" { clk } "NODE_NAME" } "" } } { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/datecontrol.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 1.800 ns disp_select\[2\]~reg0 2 REG LC3 2 " "Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC3; Fanout = 2; REG Node = 'disp_select\[2\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "0.500 ns" { clk disp_select[2]~reg0 } "NODE_NAME" } "" } } { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/datecontrol.v" 51 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.800 ns 100.00 % " "Info: Total cell delay = 1.800 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "1.800 ns" { clk disp_select[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { clk clk~out disp_select[2]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "1.800 ns" { clk disp_select[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { clk clk~out disp_select[2]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "1.800 ns" { clk disp_select[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { clk clk~out disp_select[2]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.200 ns + " "Info: + Micro clock to output delay of source is 1.200 ns" {  } { { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/datecontrol.v" 51 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/datecontrol.v" 51 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "3.700 ns" { disp_select[2]~reg0 disp_select[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.700 ns" { disp_select[2]~reg0 disp_select[2]~reg0 } { 0.000ns 1.100ns } { 0.000ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "1.800 ns" { clk disp_select[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { clk clk~out disp_select[2]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "1.800 ns" { clk disp_select[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { clk clk~out disp_select[2]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "month1\[2\]~reg0 Date_EN clk 3.200 ns register " "Info: tsu for register \"month1\[2\]~reg0\" (data pin = \"Date_EN\", clock pin = \"clk\") is 3.200 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.200 ns + Longest pin register " "Info: + Longest pin to register delay is 4.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns Date_EN 1 PIN PIN_85 55 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_85; Fanout = 55; PIN Node = 'Date_EN'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "" { Date_EN } "NODE_NAME" } "" } } { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/datecontrol.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(2.600 ns) 4.200 ns month1\[2\]~reg0 2 REG LC53 3 " "Info: 2: + IC(1.400 ns) + CELL(2.600 ns) = 4.200 ns; Loc. = LC53; Fanout = 3; REG Node = 'month1\[2\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "4.000 ns" { Date_EN month1[2]~reg0 } "NODE_NAME" } "" } } { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/datecontrol.v" 51 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 66.67 % " "Info: Total cell delay = 2.800 ns ( 66.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 33.33 % " "Info: Total interconnect delay = 1.400 ns ( 33.33 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "4.200 ns" { Date_EN month1[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.200 ns" { Date_EN Date_EN~out month1[2]~reg0 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.200ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/datecontrol.v" 51 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.800 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clk 1 CLK PIN_87 20 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_87; Fanout = 20; CLK Node = 'clk'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "" { clk } "NODE_NAME" } "" } } { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/datecontrol.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 1.800 ns month1\[2\]~reg0 2 REG LC53 3 " "Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC53; Fanout = 3; REG Node = 'month1\[2\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "0.500 ns" { clk month1[2]~reg0 } "NODE_NAME" } "" } } { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/datecontrol.v" 51 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.800 ns 100.00 % " "Info: Total cell delay = 1.800 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "1.800 ns" { clk month1[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { clk clk~out month1[2]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "4.200 ns" { Date_EN month1[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.200 ns" { Date_EN Date_EN~out month1[2]~reg0 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.200ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol_cmp.qrpt" Compiler "datecontrol" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/db/datecontrol.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/date/datecontrol/" "" "1.800 ns" { clk month1[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { clk clk~out month1[2]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0}