datecontrol.map.summary

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

Flow Status : Successful - Thu Jul 13 20:12:38 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : datecontrol
Top-level Entity Name : datecontrol
Family : MAX7000S
Met timing requirements : N/A
Total macrocells : 22
Total pins : 60