setdate.fit.summary

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

Flow Status : Successful - Thu Jul 13 14:01:45 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : setdate
Top-level Entity Name : setdate
Family : MAX7000S
Met timing requirements : N/A
Total macrocells : 18 / 32 ( 56 % )
Total pins : 25 / 36 ( 69 % )
Device : EPM7032SLC44-5
Timing Models : Final