setdate.v

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

module setdate(EN2,SW1,SW2,disp_drive,month_set1,month_set0,day_set1,day_set0);

output [1:0] disp_drive;
output [3:0] month_set1,month_set0,day_set1,day_set0;
input  EN2;	//EN2为手动设置日期使能
input  SW1,SW2;

reg [1:0] disp_drive;
reg [3:0] month_set1,month_set0,day_set1,day_set0;//存放设置的日期值


always @(posedge SW1) 
//手动设置使能	
begin
  if(EN2 == 1'b1)
    begin
	  if(disp_drive < 2'b11)
	    disp_drive <= disp_drive + 2'b1;
	  else
	    disp_drive <= 2'b0;
	end
end

always @(posedge SW2)
begin
  case(disp_drive)
    2'b00: begin
	         if(month_set1 < 4'b0010)
	           month_set1 <= month_set1 + 4'b1;
	         else
		       month_set1 <= 4'b0;
    	   end
    2'b01: begin
   		     if(month_set0 < 4'b1001)
			   month_set0 <= month_set0 + 4'b1;
			 else
			   month_set0 <= 4'b0;
    	   end
	2'b10: begin
			 if(day_set1 < 4'b0011)
			   day_set1 <= day_set1 + 4'b1;
			 else
			   day_set1 <= 4'b0;
    	   end
	2'b11: begin
		     if(day_set0 < 4'b1001)
		       day_set0 <= day_set0 + 4'b1;
		     else
		       day_set0 <= 4'b0;
    	  end
  endcase
end

endmodule