setdate.tan.rpt

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:month_set0_rtl_1|dffs[2] ; lpm_counter:month_set0_rtl_1|dffs[3] ; SW2        ; SW2      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:month_set0_rtl_1|dffs[1] ; lpm_counter:month_set0_rtl_1|dffs[3] ; SW2        ; SW2      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:month_set0_rtl_1|dffs[0] ; lpm_counter:month_set0_rtl_1|dffs[0] ; SW2        ; SW2      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:month_set0_rtl_1|dffs[3] ; lpm_counter:month_set0_rtl_1|dffs[0] ; SW2        ; SW2      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:month_set0_rtl_1|dffs[2] ; lpm_counter:month_set0_rtl_1|dffs[0] ; SW2        ; SW2      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:month_set0_rtl_1|dffs[1] ; lpm_counter:month_set0_rtl_1|dffs[0] ; SW2        ; SW2      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:month_set1_rtl_0|dffs[0] ; lpm_counter:month_set1_rtl_0|dffs[1] ; SW2        ; SW2      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:month_set1_rtl_0|dffs[1] ; lpm_counter:month_set1_rtl_0|dffs[1] ; SW2        ; SW2      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:month_set1_rtl_0|dffs[0] ; lpm_counter:month_set1_rtl_0|dffs[0] ; SW2        ; SW2      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:month_set1_rtl_0|dffs[1] ; lpm_counter:month_set1_rtl_0|dffs[0] ; SW2        ; SW2      ; None                        ; None                      ; 3.600 ns                ;
+-------+----------------------------------+--------------------------------------+--------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+--------------------------------------------------------------------------+
; tsu                                                                      ;
+-------+--------------+------------+------+--------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To                 ; To Clock ;
+-------+--------------+------------+------+--------------------+----------+
; N/A   ; None         ; 3.300 ns   ; EN2  ; disp_drive[0]~reg0 ; SW1      ;
; N/A   ; None         ; 3.300 ns   ; EN2  ; disp_drive[1]~reg0 ; SW1      ;
+-------+--------------+------------+------+--------------------+----------+


+-------------------------------------------------------------------------------------------------------+
; tco                                                                                                   ;
+-------+--------------+------------+--------------------------------------+---------------+------------+
; Slack ; Required tco ; Actual tco ; From                                 ; To            ; From Clock ;
+-------+--------------+------------+--------------------------------------+---------------+------------+
; N/A   ; None         ; 2.800 ns   ; lpm_counter:day_set0_rtl_3|dffs[3]   ; day_set0[3]   ; SW2        ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:month_set0_rtl_1|dffs[3] ; month_set0[3] ; SW2        ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:day_set0_rtl_3|dffs[2]   ; day_set0[2]   ; SW2        ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:month_set0_rtl_1|dffs[2] ; month_set0[2] ; SW2        ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:day_set0_rtl_3|dffs[1]   ; day_set0[1]   ; SW2        ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:day_set1_rtl_2|dffs[1]   ; day_set1[1]   ; SW2        ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:month_set0_rtl_1|dffs[1] ; month_set0[1] ; SW2        ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:month_set1_rtl_0|dffs[1] ; month_set1[1] ; SW2        ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:day_set0_rtl_3|dffs[0]   ; day_set0[0]   ; SW2        ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:day_set1_rtl_2|dffs[0]   ; day_set1[0]   ; SW2        ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:month_set0_rtl_1|dffs[0] ; month_set0[0] ; SW2        ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:month_set1_rtl_0|dffs[0] ; month_set1[0] ; SW2        ;
; N/A   ; None         ; 2.800 ns   ; disp_drive[1]~reg0                   ; disp_drive[1] ; SW1        ;
; N/A   ; None         ; 2.800 ns   ; disp_drive[0]~reg0                   ; disp_drive[0] ; SW1        ;
+-------+--------------+------------+--------------------------------------+---------------+------------+


+--------------------------------------------------------------------------------+
; th                                                                             ;
+---------------+-------------+-----------+------+--------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To                 ; To Clock ;
+---------------+-------------+-----------+------+--------------------+----------+
; N/A           ; None        ; -0.800 ns ; EN2  ; disp_drive[0]~reg0 ; SW1      ;
; N/A           ; None        ; -0.800 ns ; EN2  ; disp_drive[1]~reg0 ; SW1      ;
+---------------+-------------+-----------+------+--------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Thu Jul 13 14:01:50 2006
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off setdate -c setdate
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "SW1" is an undefined clock
    Info: Assuming node "SW2" is an undefined clock
Info: Clock "SW1" has Internal fmax of 175.44 MHz between source register "disp_drive[0]~reg0" and destination register "disp_drive[1]~reg0" (period= 5.7 ns)
    Info: + Longest register to register delay is 3.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6; Fanout = 15; REG Node = 'disp_drive[0]~reg0'
        Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC7; Fanout = 14; REG Node = 'disp_drive[1]~reg0'
        Info: Total cell delay = 2.600 ns ( 72.22 % )
        Info: Total interconnect delay = 1.000 ns ( 27.78 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "SW1" to destination register is 1.300 ns
            Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 2; CLK Node = 'SW1'
            Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC7; Fanout = 14; REG Node = 'disp_drive[1]~reg0'
            Info: Total cell delay = 1.300 ns ( 100.00 % )
        Info: - Longest clock path from clock "SW1" to source register is 1.300 ns
            Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 2; CLK Node = 'SW1'
            Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC6; Fanout = 15; REG Node = 'disp_drive[0]~reg0'
            Info: Total cell delay = 1.300 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.300 ns
    Info: + Micro setup delay of destination is 0.800 ns
Info: Clock "SW2" has Internal fmax of 175.44 MHz between source register "lpm_counter:day_set1_rtl_2|dffs[0]" and destination register "lpm_counter:day_set1_rtl_2|dffs[1]" (period= 5.7 ns)
    Info: + Longest register to register delay is 3.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 3; REG Node = 'lpm_counter:day_set1_rtl_2|dffs[0]'
        Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC12; Fanout = 2; REG Node = 'lpm_counter:day_set1_rtl_2|dffs[1]'
        Info: Total cell delay = 2.600 ns ( 72.22 % )
        Info: Total interconnect delay = 1.000 ns ( 27.78 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "SW2" to destination register is 1.300 ns
            Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_2; Fanout = 12; CLK Node = 'SW2'
            Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC12; Fanout = 2; REG Node = 'lpm_counter:day_set1_rtl_2|dffs[1]'
            Info: Total cell delay = 1.300 ns ( 100.00 % )
        Info: - Longest clock path from clock "SW2" to source register is 1.300 ns
            Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_2; Fanout = 12; CLK Node = 'SW2'
            Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC3; Fanout = 3; REG Node = 'lpm_counter:day_set1_rtl_2|dffs[0]'
            Info: Total cell delay = 1.300 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.300 ns
    Info: + Micro setup delay of destination is 0.800 ns
Info: tsu for register "disp_drive[0]~reg0" (data pin = "EN2", clock pin = "SW1") is 3.300 ns
    Info: + Longest pin to register delay is 3.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_24; Fanout = 2; PIN Node = 'EN2'
        Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.800 ns; Loc. = LC6; Fanout = 15; REG Node = 'disp_drive[0]~reg0'
        Info: Total cell delay = 2.800 ns ( 73.68 % )
        Info: Total interconnect delay = 1.000 ns ( 26.32 % )
    Info: + Micro setup delay of destination is 0.800 ns
    Info: - Shortest clock path from clock "SW1" to destination register is 1.300 ns
        Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 2; CLK Node = 'SW1'
        Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC6; Fanout = 15; REG Node = 'disp_drive[0]~reg0'
        Info: Total cell delay = 1.300 ns ( 100.00 % )
Info: tco from clock "SW2" to destination pin "day_set0[3]" through register "lpm_counter:day_set0_rtl_3|dffs[3]" is 2.800 ns
    Info: + Longest clock path from clock "SW2" to source register is 1.300 ns
        Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_2; Fanout = 12; CLK Node = 'SW2'
        Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC2; Fanout = 8; REG Node = 'lpm_counter:day_set0_rtl_3|dffs[3]'
        Info: Total cell delay = 1.300 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.300 ns
    Info: + Longest register to pin delay is 0.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 8; REG Node = 'lpm_counter:day_set0_rtl_3|dffs[3]'
        Info: 2: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_5; Fanout = 0; PIN Node = 'day_set0[3]'
        Info: Total cell delay = 0.200 ns ( 100.00 % )
Info: th for register "disp_drive[0]~reg0" (data pin = "EN2", clock pin = "SW1") is -0.800 ns
    Info: + Longest clock path from clock "SW1" to destination register is 1.300 ns
        Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 2; CLK Node = 'SW1'
        Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC6; Fanout = 15; REG Node = 'disp_drive[0]~reg0'
        Info: Total cell delay = 1.300 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 1.700 ns
    Info: - Shortest pin to register delay is 3.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_24; Fanout = 2; PIN Node = 'EN2'
        Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.800 ns; Loc. = LC6; Fanout = 15; REG Node = 'disp_drive[0]~reg0'
        Info: Total cell delay = 2.800 ns ( 73.68 % )
        Info: Total interconnect delay = 1.000 ns ( 26.32 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu Jul 13 14:01:52 2006
    Info: Elapsed time: 00:00:02