time_mux.tan.qmsg

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jul 15 17:24:42 2006 " "Info: Processing started: Sat Jul 15 17:24:42 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off time_mux -c time_mux " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off time_mux -c time_mux" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "TimeSet_EN second_0\[0\] 6.200 ns Longest " "Info: Longest tpd from source pin \"TimeSet_EN\" to destination pin \"second_0\[0\]\" is 6.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns TimeSet_EN 1 PIN PIN_85 48 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_85; Fanout = 48; PIN Node = 'TimeSet_EN'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_mux/db/time_mux_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_mux/db/time_mux_cmp.qrpt" Compiler "time_mux" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_mux/db/time_mux.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_mux/" "" "" { TimeSet_EN } "NODE_NAME" } "" } } { "time_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_mux/time_mux.v" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(4.000 ns) 5.800 ns second_0~39 2 COMB LC33 1 " "Info: 2: + IC(1.600 ns) + CELL(4.000 ns) = 5.800 ns; Loc. = LC33; Fanout = 1; COMB Node = 'second_0~39'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_mux/db/time_mux_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_mux/db/time_mux_cmp.qrpt" Compiler "time_mux" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_mux/db/time_mux.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_mux/" "" "5.600 ns" { TimeSet_EN second_0~39 } "NODE_NAME" } "" } } { "time_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_mux/time_mux.v" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 6.200 ns second_0\[0\] 3 PIN PIN_25 0 " "Info: 3: + IC(0.000 ns) + CELL(0.400 ns) = 6.200 ns; Loc. = PIN_25; Fanout = 0; PIN Node = 'second_0\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_mux/db/time_mux_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_mux/db/time_mux_cmp.qrpt" Compiler "time_mux" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_mux/db/time_mux.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_mux/" "" "0.400 ns" { second_0~39 second_0[0] } "NODE_NAME" } "" } } { "time_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_mux/time_mux.v" 15 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.600 ns 74.19 % " "Info: Total cell delay = 4.600 ns ( 74.19 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns 25.81 % " "Info: Total interconnect delay = 1.600 ns ( 25.81 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_mux/db/time_mux_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_mux/db/time_mux_cmp.qrpt" Compiler "time_mux" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_mux/db/time_mux.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_mux/" "" "6.200 ns" { TimeSet_EN second_0~39 second_0[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.200 ns" { TimeSet_EN TimeSet_EN~out second_0~39 second_0[0] } { 0.000ns 0.000ns 1.600ns 0.000ns } { 0.000ns 0.200ns 4.000ns 0.400ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jul 15 17:24:42 2006 " "Info: Processing ended: Sat Jul 15 17:24:42 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}