time_mux.hier_info

基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码

|time_mux
TimeSet_EN => hour_1~0.OUTPUTSELECT
TimeSet_EN => hour_1~1.OUTPUTSELECT
TimeSet_EN => hour_1~2.OUTPUTSELECT
TimeSet_EN => hour_1~3.OUTPUTSELECT
TimeSet_EN => hour_0~0.OUTPUTSELECT
TimeSet_EN => hour_0~1.OUTPUTSELECT
TimeSet_EN => hour_0~2.OUTPUTSELECT
TimeSet_EN => hour_0~3.OUTPUTSELECT
TimeSet_EN => minute_1~0.OUTPUTSELECT
TimeSet_EN => minute_1~1.OUTPUTSELECT
TimeSet_EN => minute_1~2.OUTPUTSELECT
TimeSet_EN => minute_1~3.OUTPUTSELECT
TimeSet_EN => minute_0~0.OUTPUTSELECT
TimeSet_EN => minute_0~1.OUTPUTSELECT
TimeSet_EN => minute_0~2.OUTPUTSELECT
TimeSet_EN => minute_0~3.OUTPUTSELECT
TimeSet_EN => second_1~0.OUTPUTSELECT
TimeSet_EN => second_1~1.OUTPUTSELECT
TimeSet_EN => second_1~2.OUTPUTSELECT
TimeSet_EN => second_1~3.OUTPUTSELECT
TimeSet_EN => second_0~0.OUTPUTSELECT
TimeSet_EN => second_0~1.OUTPUTSELECT
TimeSet_EN => second_0~2.OUTPUTSELECT
TimeSet_EN => second_0~3.OUTPUTSELECT
hour1[0] => hour_1~3.DATAA
hour1[1] => hour_1~2.DATAA
hour1[2] => hour_1~1.DATAA
hour1[3] => hour_1~0.DATAA
hour0[0] => hour_0~3.DATAA
hour0[1] => hour_0~2.DATAA
hour0[2] => hour_0~1.DATAA
hour0[3] => hour_0~0.DATAA
minute1[0] => minute_1~3.DATAA
minute1[1] => minute_1~2.DATAA
minute1[2] => minute_1~1.DATAA
minute1[3] => minute_1~0.DATAA
minute0[0] => minute_0~3.DATAA
minute0[1] => minute_0~2.DATAA
minute0[2] => minute_0~1.DATAA
minute0[3] => minute_0~0.DATAA
second1[0] => second_1~3.DATAA
second1[1] => second_1~2.DATAA
second1[2] => second_1~1.DATAA
second1[3] => second_1~0.DATAA
second0[0] => second_0~3.DATAA
second0[1] => second_0~2.DATAA
second0[2] => second_0~1.DATAA
second0[3] => second_0~0.DATAA
hour_set1[0] => hour_1~3.DATAB
hour_set1[1] => hour_1~2.DATAB
hour_set1[2] => hour_1~1.DATAB
hour_set1[3] => hour_1~0.DATAB
hour_set0[0] => hour_0~3.DATAB
hour_set0[1] => hour_0~2.DATAB
hour_set0[2] => hour_0~1.DATAB
hour_set0[3] => hour_0~0.DATAB
minute_set1[0] => minute_1~3.DATAB
minute_set1[1] => minute_1~2.DATAB
minute_set1[2] => minute_1~1.DATAB
minute_set1[3] => minute_1~0.DATAB
minute_set0[0] => minute_0~3.DATAB
minute_set0[1] => minute_0~2.DATAB
minute_set0[2] => minute_0~1.DATAB
minute_set0[3] => minute_0~0.DATAB
second_set1[0] => second_1~3.DATAB
second_set1[1] => second_1~2.DATAB
second_set1[2] => second_1~1.DATAB
second_set1[3] => second_1~0.DATAB
second_set0[0] => second_0~3.DATAB
second_set0[1] => second_0~2.DATAB
second_set0[2] => second_0~1.DATAB
second_set0[3] => second_0~0.DATAB
hour_1[0] <= hour_1~3.DB_MAX_OUTPUT_PORT_TYPE
hour_1[1] <= hour_1~2.DB_MAX_OUTPUT_PORT_TYPE
hour_1[2] <= hour_1~1.DB_MAX_OUTPUT_PORT_TYPE
hour_1[3] <= hour_1~0.DB_MAX_OUTPUT_PORT_TYPE
hour_0[0] <= hour_0~3.DB_MAX_OUTPUT_PORT_TYPE
hour_0[1] <= hour_0~2.DB_MAX_OUTPUT_PORT_TYPE
hour_0[2] <= hour_0~1.DB_MAX_OUTPUT_PORT_TYPE
hour_0[3] <= hour_0~0.DB_MAX_OUTPUT_PORT_TYPE
minute_1[0] <= minute_1~3.DB_MAX_OUTPUT_PORT_TYPE
minute_1[1] <= minute_1~2.DB_MAX_OUTPUT_PORT_TYPE
minute_1[2] <= minute_1~1.DB_MAX_OUTPUT_PORT_TYPE
minute_1[3] <= minute_1~0.DB_MAX_OUTPUT_PORT_TYPE
minute_0[0] <= minute_0~3.DB_MAX_OUTPUT_PORT_TYPE
minute_0[1] <= minute_0~2.DB_MAX_OUTPUT_PORT_TYPE
minute_0[2] <= minute_0~1.DB_MAX_OUTPUT_PORT_TYPE
minute_0[3] <= minute_0~0.DB_MAX_OUTPUT_PORT_TYPE
second_1[0] <= second_1~3.DB_MAX_OUTPUT_PORT_TYPE
second_1[1] <= second_1~2.DB_MAX_OUTPUT_PORT_TYPE
second_1[2] <= second_1~1.DB_MAX_OUTPUT_PORT_TYPE
second_1[3] <= second_1~0.DB_MAX_OUTPUT_PORT_TYPE
second_0[0] <= second_0~3.DB_MAX_OUTPUT_PORT_TYPE
second_0[1] <= second_0~2.DB_MAX_OUTPUT_PORT_TYPE
second_0[2] <= second_0~1.DB_MAX_OUTPUT_PORT_TYPE
second_0[3] <= second_0~0.DB_MAX_OUTPUT_PORT_TYPE